| Power estimation methodology for a high-level synthesis framework S Ahuja, DA Mathaikutty, G Singh, J Stetzer, SK Shukla, A Dingankar 2009 10th International Symposium on Quality Electronic Design, 541-546, 2009 | 47 | 2009 |
| Model-driven test generation for system level validation DA Mathaikutty, S Ahuja, A Dingankar, S Shukla 2007 IEEE International High Level Design Validation and Test Workshop, 83-90, 2007 | 38 | 2007 |
| High level power estimation models for FPGAs A Lakshminarayana, S Ahuja, S Shukla 2011 IEEE Computer Society Annual Symposium on VLSI, 7-12, 2011 | 32 | 2011 |
| Hardware coprocessor synthesis from an ansi c specification S Ahuja, ST Gurumani, C Spackman, SK Shukla IEEE Design & Test of Computers 26 (4), 58-67, 2009 | 30 | 2009 |
| MCBCG: Model checking based sequential clock-gating S Ahuja, S Shukla 2009 IEEE International High Level Design Validation and Test Workshop, 20-25, 2009 | 22 | 2009 |
| High level power estimation and reduction techniques for power aware hardware design S Ahuja Virginia Tech, 2010 | 19 | 2010 |
| The model checking view to clock gating and operand isolation J Brandt, K Schneider, S Ahuja, SK Shukla 2010 10th International Conference on Application of Concurrency to System …, 2010 | 18 | 2010 |
| A methodology for power aware high-level synthesis of co-processors from software algorithms S Ahuja, W Zhang, A Lakshminarayana, SK Shukla 2010 23rd International Conference on VLSI Design, 282-287, 2010 | 17 | 2010 |
| Field programmable gate arrays based overcurrent relays S Ahuja, SK Balasubramanian Electric Power Components and Systems 32 (3), 247-255, 2004 | 15 | 2004 |
| Posterior spinal dysraphism with lumbocostovertebral syndrome G Singh, S Ahuja, R Kumar, A Chandra, B Ojha, C Singh, S Gupta British Journal of neurosurgery 24 (2), 216-218, 2010 | 14 | 2010 |
| Scope: Statistical regression based power models for co-processors power estimation S Ahuja, DA Mathaikutty, A Lakshminarayana, SK Shukla Journal of Low Power Electronics 5 (4), 407-415, 2009 | 14 | 2009 |
| Assertion-based modal power estimation S Ahuja, DA Mathaikutty, S Shukla, A Dingankar 2007 Eighth International Workshop on Microprocessor Test and Verification, 3-7, 2007 | 14 | 2007 |
| Low Power Design with High-Level Power Estimation and Power-Aware Synthesis S Ahuja, A Lakshminarayana, SK Shukla Springer Science & Business Media, 2011 | 13 | 2011 |
| Fault‐and Defect‐Tolerant Architectures for Nanocomputing S Ahuja, G Singh, D Bhaduri, S Shukla Bio‐Inspired and Nanoscale Integrated Computing, 263-293, 2009 | 13 | 2009 |
| Applying verification collaterals for accurate power estimation S Ahuja, DA Mathaikutty, S Shukla 2008 Ninth International Workshop on Microprocessor Test and Verification, 61-66, 2008 | 13 | 2008 |
| System level simulation guided approach to improve the efficacy of clock-gating S Ahuja, W Zhang, SK Shukla 2010 IEEE International High Level Design Validation and Test Workshop …, 2010 | 12 | 2010 |
| Accurate power estimation of hardware co-processors using system level simulation S Ahuja, DA Mathaikutty, A Lakshminarayana, S Shukla 2009 IEEE International SOC Conference (SOCC), 399-402, 2009 | 12 | 2009 |
| Techniques for power-aware hardware synthesis from concurrent action oriented specifications G Singh, JB Schwartz, S Ahuja, SK Shukla Journal of Low Power Electronics 3 (2), 156-166, 2007 | 9 | 2007 |
| Coprocessor design space exploration using high level synthesis A Lakshminarayana, S Ahuja, S Shukla 2010 11th International Symposium on Quality Electronic Design (ISQED), 879-884, 2010 | 8 | 2010 |
| Statistical regression based power models for co-processors for faster and accurate power estimation S Ahuja, DA Mathaikutty, A Lakshminarayana, S Shukla 22nd IEEE International SOC Conference, 399-402, 2009 | 6 | 2009 |
S. S. RaviResearch Professor, Biocomplexity Institute, University of VirginiaVerified email at virginia.edu
