| Method for controlling heterogeneous multiprocessor and multigrain parallelizing compiler H Kasahara, K Kimura, J Shirako, Y Wada, M Ito, H Shikano US Patent 8,250,548, 2012 | 126 | 2012 |
| A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications T Enomoto, Y Oka, H Shikano IEEE journal of solid-state circuits 38 (7), 1220-1226, 2003 | 99 | 2003 |
| Operating plan formulation support system and method H Shikano US Patent App. 14/299,575, 2014 | 93 | 2014 |
| Multiprocessor system and multigrain parallelizing compiler H Kasahara, K Kimura, J Shirako, M Ito, H Shikano US Patent 7,895,453, 2011 | 74 | 2011 |
| Global compiler for controlling heterogeneous multiprocessor H Kasahara, K Kimura, H Shikano US Patent 8,051,412, 2011 | 70 | 2011 |
| Multi-sensing devices cooperative recognition system H Shikano, N Irie US Patent 7,340,078, 2008 | 66 | 2008 |
| Compiler control power saving scheme for multi core processors J Shirako, N Oshiyama, Y Wada, H Shikano, K Kimura, H Kasahara International Workshop on Languages and Compilers for Parallel Computing …, 2005 | 53 | 2005 |
| Information processing device, information processing system, and information processing method H Shikano US Patent App. 13/577,555, 2012 | 42 | 2012 |
| A self-controllable-voltage-level (SVL) circuit for low-power, high-speed CMOS circuits T Enomoto, Y Oka, H Shikano, T Harada Proceedings of the 28th European Solid-State Circuits Conference, 411-414, 2002 | 41 | 2002 |
| Controlling body-bias voltage and clock frequency in a multiprocessor system for processing tasks H Shikano US Patent 8,112,754, 2012 | 40 | 2012 |
| Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding H Shikano, M Ito, M Onouchi, T Todaka, T Tsunoda, T Kodama, ... IEEE Journal of Solid-State Circuits 43 (4), 902-910, 2008 | 31 | 2008 |
| Node processing device and its processing method H Shikano, Y Ogata US Patent 8,635,263, 2014 | 21 | 2014 |
| Heterogeneous multicore processor technologies for embedded systems K Uchiyama, F Arakawa, H Kasahara, T Nojiri, H Noda, Y Tawara, ... Springer New York, 2012 | 19 | 2012 |
| Multiprocessor system H Shikano, N Irie US Patent App. 11/203,284, 2006 | 18 | 2006 |
| Multiprocessor system and multigrain parallelizing compiler H Kasahara, K Kimura, J Shirako, M Ito, H Shikano US Patent 8,812,880, 2014 | 14 | 2014 |
| Performance evaluation of heterogeneous chip multi-processor with MP3 audio encoder H Shikano, Y Suzuki, Y Wada, J Shirako, K Kimura, H Kasahara IEEE Symposium on Low-Power and High Speed Chips (COOL Chips IX), 349-363, 2006 | 13 | 2006 |
| Operation managing device and operation management method H Shikano, J Yamamoto, T Saito US Patent 8,990,372, 2015 | 11 | 2015 |
| Cloud architecture for tight interaction with the real world and deep sensor-data aggregation mechanism H Aoki, H Shikano, M Okuno, Y Ogata, H Miyamoto, Y Tsushima, T Yazaki, ... SoftCOM 2010, 18th International Conference on Software, Telecommunications …, 2010 | 11 | 2010 |
| A parallelizing compiler cooperative heterogeneous multicore processor architecture Y Wada, A Hayashi, T Masuura, J Shirako, H Nakano, H Shikano, ... Transactions on High-Performance Embedded Architectures and Compilers IV …, 2011 | 9 | 2011 |
| Packet Analysis Apparatus H Shikano US Patent App. 12/994,355, 2011 | 9 | 2011 |
