| IEEE 802.3 az: the road to energy efficient ethernet K Christensen, P Reviriego, B Nordman, M Bennett, M Mostowfi, ... IEEE Communications Magazine 48 (11), 50-56, 2010 | 497 | 2010 |
| Performance evaluation of energy efficient ethernet P Reviriego, JA Hernández, D Larrabeiti, JA Maestro IEEE Communications Letters 13 (9), 697-699, 2009 | 183 | 2009 |
| Efficient majority logic fault detection with difference-set codes for memory applications SF Liu, P Reviriego, JA Maestro IEEE transactions on very large scale integration (VLSI) systems 20 (1), 148-156, 2010 | 145 | 2010 |
| An initial evaluation of energy efficient Ethernet P Reviriego, K Christensen, J Rabanillo, JA Maestro IEEE Communications Letters 15 (5), 578-580, 2011 | 130 | 2011 |
| Burst transmission for energy-efficient ethernet P Reviriego, JA Hernadez, D Larrabeiti, JA Maestro IEEE Internet Computing 14 (4), 50-57, 2010 | 113 | 2010 |
| Adaptive cuckoo filters M Mitzenmacher, S Pontarelli, P Reviriego Journal of Experimental Algorithmics (JEA) 25, 1-20, 2020 | 109 | 2020 |
| Hamming SEC-DAED and extended hamming SEC-DED-TAED codes through selective shortening and bit placement A Sanchez-Macian, P Reviriego, JA Maestro IEEE Transactions on Device and Materials Reliability 14 (1), 574-576, 2012 | 101 | 2012 |
| Reliability analysis of memories suffering multiple bit upsets P Reviriego, JA Maestro, C Cervantes IEEE Transactions on Device and Materials Reliability 7 (4), 592-601, 2007 | 94 | 2007 |
| A methodology for automatic insertion of selective TMR in digital circuits affected by SEUs O Ruano, JA Maestro, P Reviriego IEEE Transactions on Nuclear Science 56 (4), 2091-2102, 2009 | 89 | 2009 |
| Towards understanding the interplay of generative artificial intelligence and the internet G Martínez, L Watson, P Reviriego, JA Hernández, M Juarez, R Sarkar International Workshop on Epistemic Uncertainty in Artificial Intelligence …, 2023 | 87 | 2023 |
| Fault tolerant parallel filters based on error correction codes Z Gao, P Reviriego, W Pan, Z Xu, M Zhao, J Wang, JA Maestro IEEE Transactions on very large scale integration (VLSI) systems 23 (2), 384-387, 2014 | 74 | 2014 |
| A simple analytical model for energy efficient Ethernet MA Marsan, AF Anta, V Mancuso, B Rengarajan, PR Vasallo, G Rizzo IEEE Communications Letters 15 (7), 773-775, 2011 | 74 | 2011 |
| MCU tolerance in SRAMs through low-redundancy triple adjacent error correction LJ Saiz-Adalid, P Reviriego, P Gil, S Pontarelli, JA Maestro IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (10 …, 2014 | 72 | 2014 |
| Error detection in majority logic decoding of euclidean geometry low density parity check (EG-LDPC) codes P Reviriego, JA Maestro, MF Flanagan IEEE transactions on very large scale integration (VLSI) systems 21 (1), 156-159, 2012 | 68 | 2012 |
| New protection techniques against SEUs for moving average filters in a radiation environment P Reyes, P Reviriego, JA Maestro, O Ruano IEEE Transactions on Nuclear Science 54 (4), 957-964, 2007 | 68 | 2007 |
| Matrix-based codes for adjacent error correction CA Argyrides, P Reviriego, DK Pradhan, JA Maestro IEEE Transactions on Nuclear Science 57 (4), 2106-2111, 2010 | 66 | 2010 |
| Efficient caching of TCAM rules in RAM G Levy, P Reviriego, A Kfir, S Pontarelli US Patent 10,476,794, 2019 | 63 | 2019 |
| A method to construct low delay single error correction codes for protecting data bits only P Reviriego, S Pontarelli, JA Maestro, M Ottavi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 63 | 2013 |
| Protection of memories suffering MCUs through the selection of the optimal interleaving distance P Reviriego, JA Maestro, S Baeg, SJ Wen, R Wong IEEE Transactions on Nuclear Science 57 (4), 2124-2128, 2010 | 63 | 2010 |
| Enhanced detection of double and triple adjacent errors in hamming codes through selective bit placement A Sanchez-Macian, P Reviriego, JA Maestro IEEE Transactions on Device and Materials Reliability 12 (2), 357-362, 2012 | 61 | 2012 |
Salvatore PontarelliComputer Science - SapienzaVerified email at uniroma1.it
