| Multilevel spin-orbit torque MRAMs Y Kim, X Fong, KW Kwon, MC Chen, K Roy IEEE Transactions on Electron Devices 62 (2), 561-568, 2014 | 147 | 2014 |
| Area-efficient SOT-MRAM with a Schottky diode Y Seo, KW Kwon, K Roy IEEE Electron Device Letters 37 (8), 982-985, 2016 | 122 | 2016 |
| SHE-NVFF: Spin Hall effect-based nonvolatile flip-flop for power gating architecture KW Kwon, SH Choday, Y Kim, X Fong, SP Park, K Roy IEEE Electron Device Letters 35 (4), 488-490, 2014 | 72 | 2014 |
| High performance and energy-efficient on-chip cache using dual port (1R/1W) spin-orbit torque MRAM Y Seo, KW Kwon, X Fong, K Roy IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 (3 …, 2016 | 57 | 2016 |
| AWARE (asymmetric write architecture with redundant blocks): A high write speed STT-MRAM cache architecture KW Kwon, SH Choday, Y Kim, K Roy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (4), 712-720, 2013 | 51 | 2013 |
| High-density and robust STT-MRAM array through device/circuit/architecture interactions KW Kwon, X Fong, P Wijesinghe, P Panda, K Roy IEEE Transactions on Nanotechnology 14 (6), 1024-1034, 2015 | 42 | 2015 |
| Spin-Hall magnetic random-access memory with dual read/write ports for on-chip caches Y Seo, X Fong, KW Kwon, K Roy IEEE Magnetics Letters 6, 1-4, 2015 | 29 | 2015 |
| Area Optimization Techniques for High-Density Spin-Orbit Torque MRAMs Y Seo, KW Kwon Electronics 10 (7), 792, 2021 | 22 | 2021 |
| Design of ultra high density and low power computational blocks using nano-magnets M Sharad, K Yogendra, KW Kwon, K Roy International Symposium on Quality Electronic Design (ISQED), 223-230, 2013 | 21 | 2013 |
| Optimized memory access bandwidth devices, systems, and methods for processing low spatial locality data KW Kwon, V Kozhikkottu, SP Park, A More, WP Griffin, R Pawlowski, ... US Patent App. 15/477,072, 2018 | 16 | 2018 |
| Enhanced Data Bus Invert Encoding for OR Chained Buses KW Kwon, D Somasekhar, SP Park US Patent App. 14/569,985, 2016 | 16 | 2016 |
| Area-optimized design of SOT-MRAM Y Seo, KW Kwon IEICE Electronics Express 17 (21), 20200314-20200314, 2020 | 15 | 2020 |
| Minimal aliasing single-error-correction codes for dram reliability improvement SI Pae, V Kozhikkottu, D Somasekar, W Wu, SG Ramasubramanian, ... IEEE Access 9, 29862-29869, 2021 | 13 | 2021 |
| Rowhammer attacks in dynamic random-access memory and defense methods D Kim, H Park, I Yeo, YK Lee, Y Kim, HM Lee, KW Kwon Sensors 24 (2), 592, 2024 | 12 | 2024 |
| Modeling application-level soft error effects for single-event multi-bit upsets H Cho, KW Kwon IEEE Access 7, 133485-133495, 2019 | 10 | 2019 |
| Ultra-high density, high-performance and energy-efficient all spin logic M Sharad, K Yogendra, A Gaud, KW Kwon, K Roy arXiv preprint arXiv:1308.2280, 2013 | 9 | 2013 |
| Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application Y Seo, KW Kwon Electronics 12 (20), 4223, 2023 | 8 | 2023 |
| Low-overhead mechanism to detect address faults in ECC-protected memories KW Kwon, V Kozhikkottu, D Somasekhar US Patent 10,319,461, 2019 | 8 | 2019 |
| Anticounterfeiting tags based on randomly oriented MoSx clusters enabled by capillary and Marangoni flow C Moon, P Pujar, S Gandla, B So, S Lee, D Kim, KW Kwon, S Kim Communications Materials 4 (1), 98, 2023 | 7 | 2023 |
| Low latency statistical data bus inversion for energy reduction V Kozhikkottu, SG Ramasubramanian, KW Kwon, D Somasekhar US Patent 10,853,300, 2020 | 7 | 2020 |
