| Frontier-based search for enumerating all constrained subgraphs with compressed representation J Kawahara, T Inoue, H Iwashita, S Minato IEICE Transactions on Fundamentals of Electronics, Communications and …, 2017 | 107 | 2017 |
| Automatic test program generation for pipelined processors H Iwashita, S Kowatari, T Nakata, F Hirose ICCAD 94, 580-583, 1994 | 95 | 1994 |
| CTL model checking based on forward state traversal H Iwashita, T Nakata, F Hirose Proceedings of International Conference on Computer Aided Design, 82-87, 1996 | 93 | 1996 |
| Graphillion: software library for very large sets of labeled graphs T Inoue, H Iwashita, J Kawahara, S Minato International Journal on Software Tools for Technology Transfer 18 (1), 57-66, 2016 | 78 | 2016 |
| Efficient top-down ZDD construction techniques using recursive specifications H Iwashita, S Minato Hokkaido University Division of Computer Science TCS Technical Report TCS-TR …, 2013 | 55 | 2013 |
| Forward model checking techniques oriented to buggy designs Iwashita, Nakata 1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997 | 55 | 1997 |
| Finding all solutions and instances of numberlink and slitherlink by ZDDs R Yoshinaka, T Saitoh, J Kawahara, K Tsuruma, H Iwashita, S Minato Algorithms 5 (20), 176-213, 2012 | 53 | 2012 |
| Efficient computation of the number of paths in a grid graph with minimal perfect hash functions H Iwashita, Y Nakazawa, J Kawahara, T Uno, S Minato TCS Technical Report. No. TCS-TR-A-13-64. Hokkaido University Division of …, 2013 | 32 | 2013 |
| Verification support of circuit blocks having independent clock domains H Iwashita US Patent 8,533,541, 2013 | 29 | 2013 |
| Method and apparatus for supporting verification, and computer product H Iwashita US Patent 7,464,015, 2008 | 29 | 2008 |
| Clock domain crossing verification support H Iwashita US Patent 8,407,636, 2013 | 24 | 2013 |
| Apparatus, method, and storage medium for verifying logical device H Iwashita US Patent 6,654,715, 2003 | 21 | 2003 |
| Logical device verification method and apparatus H Iwashita, T Nakata US Patent 6,141,633, 2000 | 21 | 2000 |
| Simplifying urban network security games with cut-based graph contraction H Iwashita, K Ohori, H Anai, A Iwasaki Proceedings of the 2016 International Conference on Autonomous Agents …, 2016 | 19 | 2016 |
| ZDD-based computation of the number of paths in a graph H Iwashita, J Kawahara, S Minato Hokkaido University Division of Computer Science TCS Technical Report TCSTR …, 2012 | 18 | 2012 |
| Efficient constrained pattern mining using dynamic item ordering for explainable classification H Iwashita, T Takagi, H Suzuki, K Goto, K Ohori, H Arimura arXiv preprint arXiv:2004.08015, 2020 | 14 | 2020 |
| Logic verification device, logic verification method, and computer product H Iwashita US Patent 7,194,713, 2007 | 14 | 2007 |
| System for automatic generating instruction string to verify pipeline operations of a processor by inputting specification information having time for the processor to access … H Iwashita US Patent 5,673,425, 1997 | 14 | 1997 |
| Integrated design and test assistance for pipeline controllers H Iwashita, T Nakata, F Hirose IEICE TRANSACTIONS on Information and Systems 76 (7), 747-754, 1993 | 13 | 1993 |
| Preparation and properties of castable ceramics (OCC) Y Hata, H Suzuki, H Iijima, H Yamazaki, H Iwashita, Y Hakamatsuka, ... Nihon Hotetsu Shika Gakkai zasshi 32 (1), 52-61, 1988 | 11 | 1988 |
Shin-ichi MinatoKyoto UniversityVerified email at i.kyoto-u.ac.jp
