| Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices M Gautschi, PD Schiavone, A Traber, I Loi, A Pullini, D Rossi, E Flamand, ... IEEE transactions on very large scale integration (VLSI) systems 25 (10 …, 2017 | 637 | 2017 |
| Design issues and considerations for low-cost 3-D TSV IC technology G Van der Plas, P Limaye, I Loi, A Mercha, H Oprins, C Torregiani, S Thijs, ... IEEE Journal of Solid-State Circuits 46 (1), 293-307, 2010 | 407 | 2010 |
| GAP-8: A RISC-V SoC for AI at the Edge of the IoT E Flamand, D Rossi, F Conti, I Loi, A Pullini, F Rotenberg, L Benini 2018 IEEE 29th International Conference on Application-specific Systems …, 2018 | 290 | 2018 |
| A low-overhead fault tolerance scheme for TSV-based 3D network on chip links I Loi, S Mitra, TH Lee, S Fujita, L Benini 2008 IEEE/ACM International Conference on Computer-Aided Design, 598-602, 2008 | 258 | 2008 |
| Mr. Wolf: An energy-precision scalable parallel ultra low power SoC for IoT edge processing A Pullini, D Rossi, I Loi, G Tagliavini, L Benini IEEE Journal of Solid-State Circuits 54 (7), 1970-1981, 2019 | 219 | 2019 |
| PULP: A parallel ultra low power platform for next generation IoT applications D Rossi, F Conti, A Marongiu, A Pullini, I Loi, M Gautschi, G Tagliavini, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-39, 2015 | 175 | 2015 |
| An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ... IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017 | 170 | 2017 |
| A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters A Rahimi, I Loi, MR Kakoee, L Benini 2011 Design, Automation & Test in Europe, 1-6, 2011 | 165 | 2011 |
| Neurostream: Scalable and energy efficient deep learning with smart memory cubes E Azarkhish, D Rossi, I Loi, L Benini IEEE Transactions on Parallel and Distributed Systems 29 (2), 420-434, 2017 | 156 | 2017 |
| Vega: A ten-core SoC for IoT endnodes with DNN acceleration and cognitive wake-up from MRAM-based state-retentive sleep mode D Rossi, F Conti, M Eggiman, A Di Mauro, G Tagliavini, S Mach, ... IEEE Journal of Solid-State Circuits 57 (1), 127-139, 2021 | 128 | 2021 |
| PULP: A ultra-low power parallel accelerator for energy-efficient and flexible embedded vision F Conti, D Rossi, A Pullini, I Loi, L Benini Journal of Signal Processing Systems 84 (3), 339-354, 2016 | 127 | 2016 |
| Supporting vertical links for 3d networks-on-chip: Toward an automated design and analysis flow I Loi, F Angiolini, L Benini Proceedings of the 2nd international conference on Nano-Networks, 1-5, 2007 | 90 | 2007 |
| Characterization and implementation of fault-tolerant vertical links for 3-D networks-on-chip I Loi, F Angiolini, S Fujita, S Mitra, L Benini IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 89 | 2010 |
| Energy-efficient near-threshold parallel computing: The PULPv2 cluster D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Teman, ... Ieee Micro 37 (5), 20-31, 2017 | 81 | 2017 |
| A 60 gops/w,− 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Bartolini, ... Solid-State Electronics 117, 170-184, 2016 | 81 | 2016 |
| Mr. wolf: A 1 gflop/s energy-proportional parallel ultra low power soc for iot edge processing A Pullini, D Rossi, I Loi, A Di Mauro, L Benini ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018 | 79 | 2018 |
| Developing mesochronous synchronizers to enable 3D NoCs I Loi, F Angiolini, L Benini Proceedings of the conference on Design, automation and test in Europe, 1414 …, 2008 | 69 | 2008 |
| Design and evaluation of a processing-in-memory architecture for the smart memory cube E Azarkhish, D Rossi, I Loi, L Benini International Conference on Architecture of Computing Systems, 19-31, 2016 | 68 | 2016 |
| An efficient distributed memory interface for many-core platform with 3D stacked DRAM I Loi, L Benini 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 68 | 2010 |
| 4.4 A 1.3 TOPS/W@ 32GOPS fully integrated 10-core SoC for IoT end-nodes with 1.7 μW cognitive wake-up from MRAM-based state-retentive sleep mode D Rossi, F Conti, M Eggiman, S Mach, A Di Mauro, M Guermandi, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 60-62, 2021 | 63 | 2021 |
