| CAPI: A coherent accelerator processor interface J Stuecheli, B Blaner, CR Johns, MS Siegel IBM Journal of Research and Development 59 (1), 7: 1-7: 7, 2015 | 256 | 2015 |
| IBM POWER7 multicore server processor B Sinharoy, R Kalla, WJ Starke, HQ Le, R Cargnoni, JA Van Norstrand, ... IBM Journal of Research and Development 55 (3), 1: 1-1: 29, 2011 | 241 | 2011 |
| Minimalist open-page: A DRAM page-mode scheduling policy for the many-core era D Kaseridis, J Stuecheli, LK John Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 235 | 2011 |
| The virtual write queue: Coordinating DRAM and last-level cache policies J Stuecheli, D Kaseridis, D Daly, HC Hunter, LK John ACM SIGARCH Computer Architecture News 38 (3), 72-82, 2010 | 177 | 2010 |
| Elastic refresh: Techniques to mitigate refresh penalties in high density memory J Stuecheli, D Kaseridis, HC Hunter, LK John 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 375-384, 2010 | 156 | 2010 |
| Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems J Mukundan, H Hunter, K Kim, J Stuecheli, JF Martínez ACM SIGARCH Computer Architecture News 41 (3), 48-59, 2013 | 151 | 2013 |
| The cache and memory subsystems of the IBM POWER8 processor WJ Starke, J Stuecheli, DM Daly, JS Dodson, F Auernhammer, ... IBM Journal of Research and Development 59 (1), 3: 1-3: 13, 2015 | 91 | 2015 |
| IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI J Stuecheli, WJ Starke, JD Irish, LB Arimilli, D Dreps, B Blaner, ... IBM Journal of Research and Development 62 (4/5), 8: 1-8: 8, 2018 | 68 | 2018 |
| Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state GL Guthrie, AC Sawdey, WJ Starke, JA Stuecheli US Patent 7,536,513, 2009 | 50 | 2009 |
| A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large cmp systems D Kaseridis, J Stuecheli, J Chen, LK John HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010 | 48 | 2010 |
| Bank-aware dynamic cache partitioning for multicore architectures D Kaseridis, J Stuecheli, LK John 2009 International Conference on Parallel Processing, 18-25, 2009 | 48 | 2009 |
| System bus structure for large L2 cache array topology with different latency domains VE Chung, GL Guthrie, WJ Starke, JA Stuecheli US Patent 7,469,318, 2008 | 45 | 2008 |
| Weighted history allocation predictor algorithm in a hybrid cache DM Daly, BL Goodman, SJ Powell, AC Sawdey, JA Stuecheli US Patent 8,930,625, 2015 | 44 | 2015 |
| Data processing system and method for efficient coherency communication utilizing coherency domains JS Fields Jr, GL Guthrie, WJ Starke, JA Stuecheli US Patent 8,214,600, 2012 | 42 | 2012 |
| Selective cache-to-cache lateral castouts GL Guthrie, WJ Starke, J Stuecheli, DE Williams, TR Puzak US Patent 9,189,403, 2015 | 40 | 2015 |
| Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted RH Bell, TM Capasso, GL Guthrie, H Shen, JA Stuecheli US Patent 8,352,712, 2013 | 40 | 2013 |
| Programmable bank/timer address folding in memory devices MA Brittain, WE Maule, GA Morrison, JA Stuecheli US Patent 7,516,264, 2009 | 38 | 2009 |
| Store stream prefetching in a microprocessor JB Griswell Jr, HQ Le, FP O'Connell, WJ Starke, JA Stuecheli, AT Williams US Patent 7,380,066, 2008 | 36 | 2008 |
| Minimalist open-page: A DRAM page-mode scheduling polidy for the many-core era K Dimitris, J Stuecheli, LK John 2011 44th Annual IEEE/ACM International Symposium on Michoarechtecture ACM …, 2011 | 35 | 2011 |
| Dynamic inclusive policy in a hybrid cache hierarchy using hit rate DM Daly, BL Goodman, SJ Powell, AC Sawdey, JA Stuecheli US Patent 8,788,757, 2014 | 34 | 2014 |
