| Carbon nanomaterials for next-generation interconnects and passives: Physics, status, and prospects H Li, C Xu, N Srivastava, K Banerjee IEEE Transactions on electron devices 56 (9), 1799-1821, 2009 | 575 | 2009 |
| Performance analysis of carbon nanotube interconnects for VLSI applications N Srivastava, K Banerjee ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 401 | 2005 |
| A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy GL Loi, B Agrawal, N Srivastava, SC Lin, T Sherwood, K Banerjee Proceedings of the 43rd annual Design Automation Conference, 991-996, 2006 | 270 | 2006 |
| On the applicability of single-walled carbon nanotubes as VLSI interconnects N Srivastava, H Li, F Kreupl, K Banerjee IEEE Transactions on Nanotechnology 8 (4), 542-559, 2009 | 250 | 2009 |
| Scaling analysis of multilevel interconnect temperatures for high-performance ICs S Im, N Srivastava, K Banerjee, KE Goodson IEEE Transactions on Electron Devices 52 (12), 2710-2719, 2005 | 244 | 2005 |
| Are carbon nanotubes the future of VLSI interconnections? K Banerjee, N Srivastava Proceedings of the 43rd annual design automation conference, 809-814, 2006 | 163 | 2006 |
| Carbon nanotube interconnects: implications for performance, power dissipation and thermal management N Srivastava, RV Joshi, K Banerjee IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 124 | 2005 |
| Interconnect challenges for nanoscale electronic circuits N Srivastava, K Banerjee Jom 56 (10), 30-31, 2004 | 103 | 2004 |
| A comparative scaling analysis of metallic and carbon nanotube interconnections for nanometer scale VLSI technologies N Srivastava, K Banerjee Proc. 21st Intl. VLSI Multilevel Interconnect Conf, 393-398, 2004 | 97 | 2004 |
| Introspective 3D chips S Mysore, B Agrawal, N Srivastava, SC Lin, K Banerjee, T Sherwood Proceedings of the 12th international conference on Architectural support …, 2006 | 83 | 2006 |
| Current status and future perspectives of carbon nanotube interconnects K Banerjee, H Li, N Srivastava 2008 8th IEEE Conference on Nanotechnology, 432-436, 2008 | 67 | 2008 |
| Impact of on-chip inductance on power distribution network design for nanometer scale integrated circuits N Srivastava, X Qi, K Banerjee Sixth international symposium on quality electronic design (isqed'05), 346-351, 2005 | 51 | 2005 |
| Carbon nanotube vias: Does ballistic electron–phonon transport imply improved performance and reliability? H Li, N Srivastava, JF Mao, WY Yin, K Banerjee IEEE transactions on electron devices 58 (8), 2689-2701, 2011 | 48 | 2011 |
| Interconnect modeling and analysis in the nanometer era: Cu and beyond K Banerjee, S Im, N Srivastava Proc. 22nd Adv. Metallization Conf, 26-29, 2005 | 36 | 2005 |
| Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems K Banerjee, SC Lin, N Srivastava Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 30 | 2006 |
| Carbon nanotube vias: A reality check H Li, N Srivastava, JF Mao, WY Yin, K Banerjee 2007 IEEE International Electron Devices Meeting, 207-210, 2007 | 29 | 2007 |
| A thermally-aware methodology for design-specific optimization of supply and threshold voltages in nanometer scale ICs SC Lin, N Srivastava, K Banerjee 2005 International Conference on Computer Design, 411-416, 2005 | 21 | 2005 |
| Thermal scaling analysis of multilevel Cu/Low-k interconnect structures in deep nanometer scale technologies S Im, N Srivastava, K Banerjee, K Goodson Proc. 22th Int. VLSI Multilevel Interconnect Conf.(VMIC), 525-530, 2005 | 19 | 2005 |
| Analytical expressions for high-frequency VLSI interconnect impedance extraction in the presence of a multilayer conductive substrate N Srivastava, R Suaya, K Banerjee IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 11 | 2009 |
| High-frequency mutual impedance extraction of VLSI interconnects in the presence of a multi-layer conducting substrate N Srivastava, R Suaya, K Banerjee Proceedings of the conference on Design, automation and test in Europe, 426-431, 2008 | 8 | 2008 |
Kaustav BanerjeeUC Santa Barbara, Stanford University, UC BerkeleyVerified email at ece.ucsb.edu
