| Study of Floating Body Effect in SOI Technology B Vandana International Journal of Modern Engineering Research (IJMER) 3 (3), 1817-1824, 2013 | 47 | 2013 |
| Inverted ‘T’junctionless FinFET (ITJL FinFET): performance estimation through device geometry variation B Vandana, BS Patro, JK Das, BK Kaushik, SK Mohapatra ECS Journal of Solid State Science and Technology 7 (4), Q52, 2018 | 14 | 2018 |
| 1 GHz high sensitivity differential current comparator for high speed ADC BS Patro, S Biswas, I Roy, B Vandana Journal of Digital Integrated Circuits in Electrical Devices 2 (1), 7-12, 2017 | 12 | 2017 |
| Automatic movable road divider using Arduino UNO with Node Micro Controller Unit (MCU) SSS Vastava, B Vandana, M Bhavana, R Gongati Materials Today: Proceedings 80, 1842-1845, 2023 | 11 | 2023 |
| Impact of channel engineering (si1-0.25 ge0. 25) technique on gm (transconductance) and its higher order derivatives of 3d conventional and wavy junctionless finfets (jlt) B Vandana, JK Das, SK Mohapatra, SL Tripathi Facta Universitatis, Series: Electronics and Energetics 31 (2), 257-265, 2018 | 11 | 2018 |
| Channel thickness dependency of high-k gate dielectric based double-gate CMOS inverter S Tayal, P Samrat, V Keerthi, B Vandana, S Gupta International Journal of Nano Dimension 11 (3), 2020 | 10 | 2020 |
| Memoryless nonlinearity in IT JL FinFET with spacer technology: Investigation towards reliability B Vandana, SK Mohapatra, JK Das, KP Pradhan, A Kundu, BK Kaushik Microelectronics Reliability 119, 114072, 2021 | 9 | 2021 |
| Effectiveness of High Permittivity Spacer for Underlap Regions of Wavy-Junctionless FinFET at 22 nm Node and Scaling Short Channel Effects B Vandana, JK Das, SK Mohapatra, BK Kaushik International Symposium on VLSI Design and Test, 545-556, 2017 | 6 | 2017 |
| Mole fraction dependency electrical performances of extremely thin SiGe on insulator junctionless channel transistor (SG-OI JLCT) B Vandana, P Parashar, BS Patro, KP Pradhan, SK Mohapatra, JK Das Advances in Signal Processing and Communication: Select Proceedings of ICSC …, 2018 | 4 | 2018 |
| Low Power Strategies for beyond Moore's Law Era: Low Power Device Technologies and Materials BS Patro, B Vandana Design and Modeling of Low Power VLSI Systems, 27-47, 2016 | 4 | 2016 |
| Exploration towards electrostatic integrity for SiGe on insulator (SG-OI) on junctionless channel transistor (JLCT) B Vandana, JK Das, BS Patro, SK Mohapatra Facta Universitatis, Series: Electronics and Energetics 30 (3), 383-390, 2017 | 3 | 2017 |
| Physical insight of junctionless transistor with simulation study of Strained channel B Vandana, BS Patro, JK Das, SK Mohapatra ECTI Transactions on Electrical Engineering, Electronics, and Communications …, 2017 | 3 | 2017 |
| Challenges and Limitations of Low Power Techniques: Low Power Methodologies in B Vandana, BS Patro Design and Modeling of Low Power VLSI Systems, 48, 2016 | 3 | 2016 |
| Low Power Performance Analysis of 16-Bit Vedic Math RISC Processor PSA Khan, B Vandana, MVVS Deepak, KR Baddam 2023 3rd Asian Conference on Innovation in Technology (ASIANCON), 1-6, 2023 | 2 | 2023 |
| Implementation of three stage comparator using a modified latch with sustainable resources G Navya, K Jamal, HB Valiveti, JK Gupta, B Vandana E3S Web of Conferences 430, 01012, 2023 | 1 | 2023 |
| Macromodel development for Wind Speed Estimation Using RBF-SVM BS Patro, P Swain, B Vandana 2021 IEEE 4th International Conference on Computing, Power and Communication …, 2021 | 1 | 2021 |
| Emerging Trends in Nanoscale Semiconductor Devices JKDSKM B. Vandana, B. S. Patro Advanced VLSI Design and Testability Issues, 111-127, 2020 | 1 | 2020 |
| Prospects of 2D Junctionless Channel Transistor (JLCT) Towards Analog and RF Metrics Using Si and SiGe in Device Layer B Vandana, SK Mohapatra, JK Das, BS Patro Journal of Low Power Electronics 13 (3), 536-544, 2017 | 1 | 2017 |
| Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder M Panigrahy, NC Behera, B Vandana, I Chakrabarti, AS Dhar International Symposium on VLSI Design and Test, 376-387, 2017 | 1 | 2017 |
| Impact on gate oxide material of inverted ‘T’Junctionless FinFET at 22 nm technology node B Vandana, JK Das, SK Mohapatra, MS Jyothi 2017 1st International Conference on Electronics, Materials Engineering and …, 2017 | 1 | 2017 |
B Shivalal PatroAssistant Professor, KIIT UNIVERSITYVerified email at kiit.ac.in
