| Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs X Wei, CH Yu, P Zhang, Y Chen, Y Wang, H Hu, Y Liang, J Cong Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 548 | 2017 |
| Chronos: A timing analyzer for embedded software X Li, Y Liang, T Mitra, A Roychoudhury Science of Computer Programming 69 (1-3), 56-67, 2007 | 339 | 2007 |
| Evaluating fast algorithms for convolutional neural networks on FPGAs L Lu, Y Liang, Q Xiao, S Yan 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017 | 305 | 2017 |
| C-LSTM: Enabling efficient LSTM using structured compression techniques on FPGAs S Wang, Z Li, C Ding, B Yuan, Q Qiu, Y Wang, Y Liang Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018 | 274 | 2018 |
| Flextensor: An automatic schedule exploration and optimization framework for tensor computation on heterogeneous system S Zheng, Y Liang, S Wang, R Chen, K Sheng Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 267 | 2020 |
| Timing Analysis of Concurrent Programs Running on Shared Cache Multi-cores Yun Liang, Huping Ding, Tulika Mitra, Abhik Roychoudhury, Yan Li, Vivy Suhendra Real-Time Systems Journal (RTS) 48 (6), 638-680, 2012 | 260* | 2012 |
| Exploring heterogeneous algorithms for accelerating deep convolutional neural networks on FPGAs Q Xiao, Y Liang, L Lu, S Yan, YW Tai Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 251 | 2017 |
| Sanger: A co-design framework for enabling sparse attention using reconfigurable architecture L Lu, Y Jin, H Bi, Z Luo, P Li, T Wang, Y Liang MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 201 | 2021 |
| An efficient hardware accelerator for sparse convolutional neural networks on FPGAs L Lu, J Xie, R Huang, J Zhang, W Lin, Y Liang 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019 | 200 | 2019 |
| Evaluating fast algorithms for convolutional neural networks on FPGAs Y Liang, L Lu, Q Xiao, S Yan IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019 | 192 | 2019 |
| COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications J Zhao, L Feng, S Sinha, W Zhang, Y Liang, B He 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 430-437, 2017 | 174 | 2017 |
| Coordinated static and dynamic cache bypassing for GPUs X Xie, Y Liang, Y Wang, G Sun, T Wang 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 173 | 2015 |
| Lin-analyzer: A high-level performance analysis tool for FPGA-based accelerators G Zhong, A Prakash, Y Liang, T Mitra, S Niar Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 170 | 2016 |
| Multi-level context ultra-aggregation for stereo matching GY Nie, MM Cheng, Y Liu, Z Liang, DP Fan, Y Liu, Y Wang Proceedings of the IEEE/CVF conference on computer vision and pattern …, 2019 | 148 | 2019 |
| SpWA: An efficient sparse winograd convolutional neural networks accelerator on FPGAs L Lu, Y Liang Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 143 | 2018 |
| REQ-YOLO: A resource-aware, efficient quantization framework for object detection on FPGAs C Ding, S Wang, N Liu, K Xu, Y Wang, Y Liang proceedings of the 2019 ACM/SIGDA international symposium on field …, 2019 | 140 | 2019 |
| An efficient compiler framework for cache bypassing on GPUs X Xie, Y Liang, G Sun, D Chen Computer-Aided Design (ICCAD), 2013 IEEE/ACM International Conference on …, 2013 | 126 | 2013 |
| Improving high level synthesis optimization opportunity through polyhedral transformations W Zuo, Y Liang, P Li, K Rupnow, D Chen, J Cong Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2013 | 126 | 2013 |
| Efficient GPU spatial-temporal multitasking Y Liang, HP Huynh, K Rupnow, RSM Goh, D Chen IEEE Transactions on Parallel and Distributed Systems 26 (3), 748-760, 2014 | 117 | 2014 |
| High‐Level Synthesis: Productivity, Performance, and Software Constraints Y Liang, K Rupnow, Y Li, D Min, MN Do, D Chen Journal of Electrical and Computer Engineering 2012 (1), 649057, 2012 | 116 | 2012 |
Tulika MitraProfessor of Computer Science, National University of SingaporeVerified email at comp.nus.edu.sg
