| Performance evaluation and design trade-offs for network-on-chip interconnect architectures PP Pande, C Grecu, M Jones, A Ivanov, R Saleh IEEE transactions on Computers 54 (8), 1025-1040, 2005 | 1167 | 2005 |
| Networks-on-chip in a three-dimensional environment: A performance evaluation BS Feero, PP Pande IEEE Transactions on computers 58 (1), 32-45, 2008 | 655 | 2008 |
| System-on-chip: Reuse and integration R Saleh, S Wilton, S Mirabbasi, A Hu, M Greenstreet, G Lemieux, ... Proceedings of the IEEE 94 (6), 1050-1069, 2006 | 431 | 2006 |
| Wireless NoC as interconnection backbone for multicore chips: Promises and challenges S Deb, A Ganguly, PP Pande, B Belzer, D Heo IEEE Journal on emerging and selected topics in circuits and systems 2 (2 …, 2012 | 401 | 2012 |
| Scalable hybrid wireless network-on-chip architectures for multicore systems A Ganguly, K Chang, S Deb, PP Pande, B Belzer, C Teuscher IEEE Transactions on Computers 60 (10), 1485-1502, 2010 | 392 | 2010 |
| Design of a switch for network on chip applications PP Pande, C Grecu, A Ivanov, R Saleh 2003 IEEE International Symposium on Circuits and Systems (ISCAS) 5, V-V, 2003 | 292 | 2003 |
| Design of an energy-efficient CMOS-compatible NoC architecture with millimeter-wave wireless interconnects S Deb, K Chang, X Yu, SP Sah, M Cosic, A Ganguly, PP Pande, B Belzer, ... IEEE Transactions on Computers 62 (12), 2382-2396, 2012 | 253 | 2012 |
| Networks-on-chip in emerging interconnect paradigms: Advantages and challenges LP Carloni, P Pande, Y Xie 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 93-102, 2009 | 252 | 2009 |
| Design, synthesis, and test of networks on chips PP Pande, C Grecu, A Ivanov, R Saleh, G De Micheli IEEE Design & Test of Computers 22 (5), 404-413, 2005 | 248 | 2005 |
| Performance evaluation and design trade-offs for wireless network-on-chip architectures K Chang, S Deb, A Ganguly, X Yu, SP Sah, PP Pande, B Belzer, D Heo ACM Journal on Emerging Technologies in Computing Systems (JETC) 8 (3), 1-25, 2012 | 163 | 2012 |
| Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects A Ganguly, PP Pande, B Belzer IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (11 …, 2009 | 140 | 2009 |
| Architecture and design of multichannel millimeter-wave wireless NoC X Yu, J Baylon, P Wettin, D Heo, PP Pande, S Mirabbasi IEEE Design & Test 31 (6), 19-28, 2014 | 134 | 2014 |
| BIST for network-on-chip interconnect infrastructures C Grecu, P Pande, A Ivanov, R Saleh 24th IEEE VLSI Test Symposium, 6 pp.-35, 2006 | 131 | 2006 |
| Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects S Deb, A Ganguly, K Chang, P Pande, B Beizer, D Heo ASAP 2010-21st IEEE International Conference on Application-specific Systems …, 2010 | 127 | 2010 |
| A 1.2-pJ/bit 16-Gb/s 60-GHz OOK transmitter in 65-nm CMOS for wireless network-on-chip X Yu, SP Sah, H Rashtian, S Mirabbasi, PP Pande, D Heo IEEE Transactions on Microwave Theory and Techniques 62 (10), 2357-2369, 2014 | 121 | 2014 |
| On-line fault detection and location for NoC interconnects C Grecu, A Ivanov, R Saleh, ES Sogomonyan, PP Pande 12th IEEE International On-Line Testing Symposium (IOLTS'06), 6 pp., 2006 | 116 | 2006 |
| On-chip communication network for efficient training of deep convolutional networks on heterogeneous manycore systems W Choi, K Duraisamy, RG Kim, JR Doppa, PP Pande, D Marculescu, ... IEEE Transactions on Computers 67 (5), 672-686, 2017 | 111 | 2017 |
| Performance evaluation for three-dimensional networks-on-chip B Feero, PP Pande IEEE Computer Society Annual Symposium on VLSI (ISVLSI'07), 305-310, 2007 | 103 | 2007 |
| Testing network-on-chip communication fabrics C Grecu, A Ivanov, R Saleh, PP Pande IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 99 | 2007 |
| Design-space exploration and optimization of an energy-efficient and reliable 3-D small-world network-on-chip S Das, JR Doppa, PP Pande, K Chakrabarty IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 92 | 2016 |
Janardhan Rao (Jana) DoppaHuie-Rogers Endowed Chair Professor of CS, Washington State UniversityVerified email at eecs.wsu.edu
