| A graph placement methodology for fast chip design A Mirhoseini, A Goldie, M Yazgan, JW Jiang, E Songhori, S Wang, YJ Lee, ... Nature 594 (7862), 207-212, 2021 | 889 | 2021 |
| Chip placement with deep reinforcement learning A Mirhoseini, A Goldie, M Yazgan, J Jiang, E Songhori, S Wang, YJ Lee, ... arXiv preprint arXiv:2004.10746, 2020 | 326 | 2020 |
| Modeling of electromigration in through-silicon-via based 3D IC J Pak, M Pathak, SK Lim, DZ Pan Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, 1420 …, 2011 | 94 | 2011 |
| Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs M Pathak, J Pak, DZ Pan, SK Lim 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 555-562, 2011 | 64 | 2011 |
| Design for manufacturability and reliability for TSV-based 3D ICs DZ Pan, SK Lim, K Athikulwongse, M Jung, J Mitra, J Pak, M Pathak, ... Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific …, 2012 | 41 | 2012 |
| Electromigration study for multiscale power/ground vias in TSV-based 3-D ICs J Pak, SK Lim, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 40 | 2014 |
| Robust clock tree synthesis with timing yield optimization for 3D-ICs JS Yang, J Pak, X Zhao, SK Lim, DZ Pan 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 621-626, 2011 | 37 | 2011 |
| Electromigration-aware redundant via insertion J Pak, B Yu, DZ Pan The 20th Asia and South Pacific Design Automation Conference, 544-549, 2015 | 22 | 2015 |
| Electromigration-aware routing for 3D ICs with stress-aware EM modeling J Pak, SK Lim, DZ Pan Proceedings of the International Conference on Computer-Aided Design, 325-332, 2012 | 20 | 2012 |
| Addendum: A graph placement methodology for fast chip design A Goldie, A Mirhoseini, M Yazgan, JW Jiang, E Songhori, S Wang, YJ Lee, ... Nature 634 (8034), E10-E11, 2024 | 11 | 2024 |
| A frequency tunable resonant clock distribution scheme using bond-wire inductor W Lee, JS Pak, J Pak, C Ryu, J Park, J Kim 2008 Electrical Design of Advanced Packaging and Systems Symposium, 24-26, 2008 | 7 | 2008 |
| Design of a 3-D SiP for T-DMB with Improvement of Sensitivity and Noise Isolation J Pak, M Ha, J Kim, D Kang, H Choi, S Kwon, K La, J Kim 2008 10th Electronics Packaging Technology Conference, 1387-1392, 2008 | 7 | 2008 |
| Soft-remote-control system based on emg signals for the intelligent sweet home JH Song, JS Han, J Pak, DJ Kim, JW Jung, ZZ Bien, H Lee 제어로봇시스템학회 국제학술대회 논문집, 1163-1168, 2005 | 6 | 2005 |
| Author Correction: A graph placement methodology for fast chip design A Mirhoseini, A Goldie, M Yazgan, JW Jiang, E Songhori, S Wang, YJ Lee, ... Nature 604 (7906), E24, 2022 | 2 | 2022 |
| A graph placement methodology for fast chip design (vol 594, pg 207, 2021) A Goldie, A Mirhoseini, M Yazgan, JW Jiang, E Songhori, S Wang, YJ Lee, ... NATURE 634 (8034), E10-E11, 2024 | 1 | 2024 |
| A graph placement methodology for fast chip design (vol 594, pg 207, 2021) A Mirhoseini, A Goldie, M Yazgan, JW Jiang, E Songhori, S Wang, YJ Lee, ... NATURE 604 (7906), E24-E24, 2022 | | 2022 |
| Electromigration modeling and layout optimization for advanced VLSI J Pak | | 2014 |
| A Frequency Clock Distribution Scheme Using Bond-Wire Inductor J Kim, W Lee, JS Pak, J Pak, C Ryu, J Park IEEE Electrical Design of Advanced Packaging and Systems Symposium, 2008 | | 2008 |
| ICLAD 2025 C Yu, M Saligane, H Tsai, V Gohil, J Han, L Stok, T Chen, V Chhabria, ... | | |
James LaudonGoogle DeepMindVerified email at google.com
