| Trading accuracy for power in a multiplier architecture P Kulkarni, P Gupta, MD Ercegovac Journal of Low Power Electronics 7 (4), 490-501, 2011 | 864 | 2011 |
| Trading accuracy for power with an underdesigned multiplier architecture P Kulkarni, P Gupta, M Ercegovac 2011 24th Internatioal Conference on VLSI Design, 346-351, 2011 | 864* | 2011 |
| Can the compressive strength of concrete be estimated from knowledge of the mixture proportions?: New insights from statistical analysis and machine learning methods BA Young, A Hall, L Pilon, P Gupta, G Sant Cement and Concrete Research 115, 379-388, 2019 | 456 | 2019 |
| Reliable on-chip systems in the nano-era: Lessons learnt and future trends J Henkel, L Bauer, N Dutt, P Gupta, S Nassif, M Shafique, M Tahoori, ... Proceedings of the 50th Annual Design Automation Conference, 1-10, 2013 | 267 | 2013 |
| Gate-length biasing for digital circuit optimization P Gupta, AB Kahng US Patent 7,441,211, 2008 | 248 | 2008 |
| Massively parallel amplitude-only Fourier neural network M Miscuglio, Z Hu, S Li, JK George, R Capanna, H Dalir, PM Bardet, ... Optica 7 (12), 1812-1819, 2020 | 244 | 2020 |
| Method for correcting a mask design layout AB Kahng, P Gupta, D Sylvester, J Yang US Patent 7,149,999, 2006 | 244 | 2006 |
| Toward a methodology for manufacturability-driven design rule exploration L Capodieci, P Gupta, AB Kahng, D Sylvester, J Yang Proceedings of the 41st annual Design Automation Conference, 311-316, 2004 | 239 | 2004 |
| Method of IC fabrication, IC mask fabrication and program product therefor P Gupta, FL Heng, MA Lavin US Patent 7,353,492, 2008 | 224 | 2008 |
| Underdesigned and opportunistic computing in presence of hardware variability P Gupta, Y Agarwal, L Dolecek, N Dutt, RK Gupta, R Kumar, S Mitra, ... IEEE Transactions on Computer-Aided Design of integrated circuits and …, 2012 | 207 | 2012 |
| Manufacturing-aware physical design P Gupta, AB Kahng ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 167 | 2003 |
| Gate-length biasing for runtime-leakage control P Gupta, AB Kahng, P Sharma, D Sylvester IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 139 | 2006 |
| Method and system for placing layout objects in a standard-cell layout P Gupta, AB Kahng, CH Park US Patent 7,640,522, 2009 | 134 | 2009 |
| Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI Y Cao, P Gupta, AB Kahng, D Sylvester, J Yang 15th Annual IEEE International ASIC/SOC Conference, 411-415, 2002 | 131 | 2002 |
| Comparative evaluation of spin-transfer-torque and magnetoelectric random access memory S Wang, H Lee, F Ebrahimi, PK Amiri, KL Wang, P Gupta IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 (2 …, 2016 | 127 | 2016 |
| Methods for gate-length biasing using annotation data P Gupta, AB Kahng US Patent 8,185,865, 2012 | 125 | 2012 |
| Selective gate-length biasing for cost-effective runtime leakage control P Gupta, AB Kahng, P Sharma, D Sylvester Proceedings of the 41st annual Design Automation Conference, 327-330, 2004 | 115 | 2004 |
| Integrated circuit logic with self compensating block delays P Gupta, FL Heng, DS Kung, DL Ostapko US Patent 7,084,476, 2006 | 110 | 2006 |
| Toward a systematic-variation aware timing methodology P Gupta, FL Heng Proceedings of the 41st annual Design Automation Conference, 321-326, 2004 | 108 | 2004 |
| Optimizing multi-GPU parallelization strategies for deep learning training S Pal, E Ebrahimi, A Zulfiqar, Y Fu, V Zhang, S Migacz, D Nellans, ... IEEE Micro 39 (5), 91-101, 2019 | 97 | 2019 |
Andrew B. KahngProfessor of CSE and ECE, UC San DiegoVerified email at eng.ucsd.edu
