| The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 494 | 2020 |
| EazyHTM: Eager-lazy hardware transactional memory S Tomić, C Perfumo, C Kulkarni, A Armejach, A Cristal, O Unsal, T Harris, ... Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009 | 160 | 2009 |
| An empirical evaluation of high-level synthesis languages and tools for database acceleration O Arcas-Abella, G Ndu, N Sonmez, M Ghasempour, A Armejach, ... 2014 24th International Conference on Field Programmable Logic and …, 2014 | 75 | 2014 |
| MUSA: a multi-level simulation approach for next-generation HPC machines T Grass, C Allande, A Armejach, A Rico, E Ayguadé, J Labarta, M Valero, ... SC'16: Proceedings of the International Conference for High Performance …, 2016 | 58 | 2016 |
| Stencil codes on a vector length agnostic architecture A Armejach, H Caminal, JM Cebrian, R González-Alberquilla, ... Proceedings of the 27th International Conference on Parallel Architectures …, 2018 | 37 | 2018 |
| Using Arm’s scalable vector extension on stencil codes A Armejach, H Caminal, JM Cebrian, R Langarita, R González-Alberquilla, ... The Journal of Supercomputing 76 (3), 2039-2062, 2020 | 35 | 2020 |
| Gem5+ rtl: A framework to enable rtl models inside a full-system simulator G López-Paradís, A Armejach, M Moretó Proceedings of the 50th International Conference on Parallel Processing, 1-11, 2021 | 28 | 2021 |
| A mess of memory system benchmarking, simulation and application profiling P Esmaili-Dokht, F Sgherzi, VS Girelli, I Boixaderas, M Carmin, A Monemi, ... 2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO), 136-152, 2024 | 22 | 2024 |
| A BF16 FMA is all you need for DNN training J Osorio, A Armejach, E Petit, G Henry, M Casas IEEE Transactions on Emerging Topics in Computing 10 (3), 1302-1314, 2022 | 22 | 2022 |
| Using a reconfigurable L1 data cache for efficient version management in hardware transactional memory A Armejach, A Seyedi, R Titos-Gil, I Hur, OS Unsal, M Valero 2011 International Conference on Parallel Architectures and Compilation …, 2011 | 22 | 2011 |
| The gem5 simulator: Version 20.0+. CoRR abs/2007.03152 (2020) J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 20 | 2020 |
| HARP: Adaptive abort recurrence prediction for hardware transactional memory A Armejach, A Negi, A Cristal, O Unsal, P Stenstrom, T Harris 20th Annual International Conference on High Performance Computing, 196-205, 2013 | 20 | 2013 |
| Efficient direct convolution using long SIMD instructions AL Santana, A Armejach, M Casas Proceedings of the 28th ACM SIGPLAN Annual Symposium on Principles and …, 2023 | 19 | 2023 |
| Design space exploration of next-generation HPC machines C Gómez, F Martınez, A Armejach, M Moretó, F Mantovani, M Casas 2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2019 | 19 | 2019 |
| Multilevel simulation-based co-design of next generation HPC microprocessors L Zaourar, M Benazouz, A Mouhagir, F Jebali, T Sassolas, JC Weill, ... 2021 International Workshop on Performance Modeling, Benchmarking and …, 2021 | 17 | 2021 |
| Hardware acceleration for query processing: leveraging FPGAs, CPUs, and memory O Arcas-Abella, A Armejach, T Hayes, GA Malazgirt, O Palomar, B Salami, ... Computing in Science & Engineering 18 (1), 80-87, 2015 | 17 | 2015 |
| Techniques to improve performance in requester-wins hardware transactional memory A Armejach, R Titos-Gil, A Negi, OS Unsal, A Cristal ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 1-25, 2013 | 16 | 2013 |
| GenArchBench: A genomics benchmark suite for arm HPC processors L López-Villellas, R Langarita-Benítez, A Badouh, V Soria-Pardos, ... Future Generation Computer Systems 157, 313-329, 2024 | 15 | 2024 |
| A tensor marshaling unit for sparse tensor algebra on general-purpose processors M Siracusa, V Soria-Pardos, F Sgherzi, J Randall, DJ Joseph, ... Proceedings of the 56th Annual IEEE/ACM International Symposium on …, 2023 | 15 | 2023 |
| Circuit design of a dual-versioning L1 data cache for optimistic concurrency A Seyedi, A Armejach, A Cristal, OS Unsal, I Hur, M Valero Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011 | 15 | 2011 |
