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Adi Fuchs
Adi Fuchs
Acceleration Architect, Speedata
Verified email at princeton.edu
Title
Cited by
Cited by
Year
Openpiton: An open source manycore research framework
J Balkind, M McKeown, Y Fu, T Nguyen, Y Zhou, A Lavrov, M Shahrad, ...
Proceedings of the The 21st ACM International Conference on Architectural …, 2016
3472016
The Accelerator Wall: Limits of Chip Specialization
A Fuchs, D Wentzlaff
Proceedings of the 25th IEEE International Symposium on High-Performance …, 2019
1062019
Disruptive prefetching: impact on side-channel attacks and cache designs
A Fuchs, RB Lee
Proceedings of the 8th ACM International Systems and Storage Conference, 1-12, 2015
522015
Loop-aware memory prefetching using code block working sets
A Fuchs, S Mannor, U Weiser, Y Etsion
2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 533-544, 2014
292014
Scaling Datacenter Accelerators With Compute-Reuse Architectures
A Fuchs, D Wentzlaff
Proceedings of the 45th Annual ACM/IEEE International Symposium on Computer …, 2018
262018
Host channel adapter with pattern-type DMA
A Shahar, N Bloch, A Fuchs
US Patent 8,751,701, 2014
252014
OpenPiton: an open source hardware platform for your research
J Balkind, M McKeown, Y Fu, T Nguyen, Y Zhou, A Lavrov, M Shahrad, ...
Communications of the ACM 62 (12), 79-87, 2019
132019
Lossless Tiling in Convolution Networks—Weight Gradient Calculation
AKS Tejas Nagendra Babu Nama, Ruddhi Chaphekar, Ram Sivaramakrishnan, Raghu ...
US Patent 11,232,360, 2022
82022
Lossless Tiling in Convolution Networks—Read-Modify-Write in Backward Pass
AKS Tejas Nagendra Babu Nama, Ruddhi Chaphekar, Ram Sivaramakrishnan, Raghu ...
US Patent 11,250,061, 2022
52022
Lossless Tiling in Convolution Networks—Section Boundaries
AKS Tejas Nagendra Babu Nama, Ruddhi Chaphekar, Ram Sivaramakrishnan, Raghu ...
US Patent 11,227,207, 2022
42022
CABLE: a CAche-Based Link Encoder for Bandwidth-starved Manycores
TM Nguyen, A Fuchs, D Wentzlaff
Proceedings of the The 51st Annual IEEE/ACM International Symposium on …, 2018
42018
OpenPit
J Balkind, M McKeown, Y Fu, T Nguyen, Y Zhou, A Lavrov, M Shahrad, ...
32016
Lossless Tiling in Convolution Networks—Padding Before Tiling, Location-Based Tiling, and Zeroing-Out
AKS Tejas Nagendra Babu Nama, Ruddhi Chaphekar, Ram Sivaramakrishnan, Raghu ...
US Patent 11,263,170, 2022
22022
Lossless tiling in convolution networks—tiling configuration between two sections
TNB Nama, R Chaphekar, R Sivaramakrishnan, R Prabhakar, S Jairath, ...
US Patent 12,511,252, 2025
12025
Lossless tiling in convolution networks—resetting overlap factor to zero at section boundaries
TNB Nama, R Chaphekar, R Sivaramakrishnan, R Prabhakar, S Jairath, ...
US Patent 12,112,250, 2024
12024
Lossless Tiling in Convolution Networks-Section Boundaries
TNB Nama, R Chaphekar, R Sivaramakrishnan, R Prabhakar, S Jairath, ...
US Patent App. 17/477,409, 2022
12022
Overcoming the Limitations of Accelerator-Centric Architectures with Memoization-Driven Specialization
A Fuchs
Princeton University, 2019
12019
The Interplay of Transistors and Accelerators
A Fuchs, D Wentzlaff
ACM SRC at MICRO-51, 2, 2018
12018
Sectioning a processing graph for an application
TNB Nama, R Chaphekar, R Sivaramakrishnan, R Prabhakar, S Jairath, ...
US Patent App. 19/316,742, 2025
2025
Lossless tiling in convolution networks—padding and re-tilling at section boundaries
TNB Nama, R Chaphekar, R Sivaramakrishnan, R Prabhakar, S Jairath, ...
US Patent 12,488,218, 2025
2025
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