| Chloride Molecular Doping Technique on 2D Materials: WS2 and MoS2 L Yang, K Majumdar, H Liu, Y Du, H Wu, M Hatzistergos, PY Hung, ... Nano letters 14 (11), 6275-6280, 2014 | 898 | 2014 |
| Vertical field-effect transistor with uniform bottom spacer J Li, K Cheng, P Xu, H Wu US Patent App. 15/830,665, 2019 | 276 | 2019 |
| Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications J Zhang, J Frougier, A Greene, X Miao, L Yu, R Vega, P Montanini, ... 2019 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2019 | 113 | 2019 |
| 20–80nm channel length InGaAs gate-all-around nanowire MOSFETs with EOT= 1.2 nm and lowest SS= 63mV/dec JJ Gu, XW Wang, H Wu, J Shao, AT Neal, MJ Manfra, RG Gordon, PD Ye 2012 International Electron Devices Meeting, 27.6. 1-27.6. 4, 2012 | 112 | 2012 |
| High-performance MoS2 field-effect transistors enabled by chloride doping: Record low contact resistance (0.5 kΩ·µm) and record high drain current (460 µA/µm) L Yang, K Majumdar, Y Du, H Liu, H Wu, M Hatzistergos, PY Hung, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 93 | 2014 |
| A 14 nm embedded stt-mram cmos technology D Edelstein, M Rizzolo, D Sil, A Dutta, J DeBrosse, M Wordeman, A Arceo, ... 2020 IEEE International Electron Devices Meeting (IEDM), 11.5. 1-11.5. 4, 2020 | 82 | 2020 |
| Vertical-transport nanosheet technology for CMOS scaling beyond lateral-transport devices H Jagannathan, B Anderson, CW Sohn, G Tsutsui, J Strane, R Xie, S Fan, ... 2021 IEEE International Electron Devices Meeting (IEDM), 26.1. 1-26.1. 4, 2021 | 70 | 2021 |
| High-performance InAlN/GaN MOSHEMTs enabled by atomic layer epitaxy MgCaO as gate dielectric H Zhou, X Lou, NJ Conrad, M Si, H Wu, S Alghamdi, S Guo, RG Gordon, ... IEEE Electron Device Letters 37 (5), 556-559, 2016 | 67 | 2016 |
| Size-Dependent-Transport Study of Gate-All-Around Nanowire MOSFETs: Impact of Quantum Confinement and Volume Inversion JJ Gu, H Wu, Y Liu, AT Neal, RG Gordon, PD Ye IEEE electron device letters 33 (7), 967-969, 2012 | 63 | 2012 |
| First demonstration of Ge nanowire CMOS circuits: Lowest SS of 64 mV/dec, highest gmax of 1057 uS/um in Ge nFETs and highest maximum voltage gain of 54 V/V in Ge CMOS inverters H Wu, W Wu, M Si, PD Ye 2015 IEEE International Electron Devices Meeting (IEDM), 2015 | 61 | 2015 |
| Parasitic resistance reduction strategies for advanced CMOS FinFETs beyond 7nm H Wu, O Gluschenkov, G Tsutsui, C Niu, K Brew, C Durfee, C Prindle, ... 2018 IEEE International Electron Devices Meeting (IEDM), 35.4. 1-35.4. 4, 2018 | 54 | 2018 |
| First experimental demonstration of Ge CMOS circuits H Wu, N Conrad, W Luo, PD Ye 2014 IEEE International Electron Devices Meeting, 9.3. 1-9.3. 4, 2014 | 50 | 2014 |
| First experimental demonstration of Ge 3D FinFET CMOS circuits H Wu, W Luo, H Zhou, M Si, J Zhang, PD Ye 2015 Symposium on VLSI Technology (VLSI Technology), T58-T59, 2015 | 46 | 2015 |
| Formation of a partial air-gap spacer CH Lee, K Cheng, H Wu, P Xu US Patent 11,011,617, 2021 | 42 | 2021 |
| Germanium nMOSFETs with recessed channel and S/D: Contact, scalability, interface, and drain current exceeding 1 A/mm H Wu, M Si, L Dong, J Gu, J Zhang, PD Ye IEEE Transactions on Electron Devices 62 (5), 1419-1426, 2015 | 40 | 2015 |
| Substrate and layout engineering to suppress self-heating in floating body transistors MAA SH Shin, S-H Kim, S Kim, H Wu, PD Ye Electron Devices Meeting (IEDM), 2016 IEEE International, 15.7. 1-15.7. 4, 2016 | 35* | 2016 |
| Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices H Wu, K Cheng, J Wang, Z Liu US Patent 10,566,246, 2020 | 34 | 2020 |
| Fully Depleted Ge CMOS Devices and Logic Circuits on Si H Wu, DY Peide IEEE Transactions on Electron Devices 63 (8), 3028-3035, 2016 | 33 | 2016 |
| Demonstration of Ge Nanowire CMOS Devices and Circuits for Ultimate Scaling H Wu, W Wu, M Si, PD Ye IEEE Transactions on Electron Devices 63 (8), 3049-3057, 2016 | 31 | 2016 |
| Gate-all-around FETs having uniform threshold voltage R Bao, D Guo, J Wang, H Wu US Patent 10,692,778, 2020 | 30 | 2020 |
Peide YeRichard J. and Mary Jo Schwartz Professor of Electrical and Computer Engineering, Purdue UniversityVerified email at purdue.edu
