| Challenging the security of logic locking schemes in the era of deep learning: A neuroevolutionary approach D Sisejkovic, F Merchant, LM Reimann, H Srivastava, A Hallawa, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 17 (3), 1-26, 2021 | 99 | 2021 |
| Deceptive logic locking for hardware integrity protection against machine learning attacks D Sisejkovic, F Merchant, LM Reimann, R Leupers IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 68 | 2021 |
| Qflow: Quantitative information flow for security-aware hardware design in verilog LM Reimann, L Hanel, D Sisejkovic, F Merchant, R Leupers 2021 IEEE 39th International Conference on Computer Design (ICCD), 603-607, 2021 | 35 | 2021 |
| Logic locking at the frontiers of machine learning: A survey on developments and opportunities D Sisejkovic, LM Reimann, E Moussavi, F Merchant, R Leupers 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration …, 2021 | 33 | 2021 |
| A secure hardware-software solution based on RISC-V, logic locking and microkernel D Šišejković, F Merchant, LM Reimann, R Leupers, M Giacometti, ... Proceedings of the 23th International Workshop on Software and Compilers for …, 2020 | 25 | 2020 |
| ZuSE Ki-Avf: application-specific AI processor for intelligent sensor signal processing in autonomous driving GB Thieu, S Gesper, G Payá-Vayá, C Riggers, O Renke, T Fiedler, ... 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 16 | 2023 |
| Scaling logic locking schemes to multi-module hardware designs D Šišejković, F Merchant, LM Reimann, R Leupers, S Kegreiß International Conference on Architecture of Computing Systems, 138-152, 2020 | 14 | 2020 |
| Andromeda: An fpga based risc-v mpsoc exploration framework F Merchant, D Sisejkovic, LM Reimann, K Yasotharan, T Grass, ... 2021 34th International Conference on VLSI Design and 2021 20th …, 2021 | 10 | 2021 |
| Quantitative information flow for hardware: Advancing the attack landscape LM Reimann, S Erdönmez, D Sisejkovic, R Leupers 2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS), 1-4, 2023 | 8 | 2023 |
| Qtflow: Quantitative timing-sensitive information flow for security-aware hardware design on rtl LM Reimann, A Prashar, C Ghinami, R Pelke, D Sisejkovic, F Merchant, ... 2024 International VLSI Symposium on Technology, Systems and Applications …, 2024 | 6 | 2024 |
| Evaluation of the RISC-V Floating Point Extensions N Zurstrassen, LM Reimann, N Bosbach, L Juenger, R Leupers DVCon Europe 2023; Design and Verification Conference and Exhibition Europe …, 2023 | 4 | 2023 |
| The impact of logic locking on confidentiality: An automated evaluation LM Reimann, E Rezunov, D Germek, L Collini, C Pilato, R Karri, ... 2025 26th International Symposium on Quality Electronic Design (ISQED), 1-8, 2025 | 2 | 2025 |
| Exploiting the lock: leveraging MiG-V's logic locking for secret-data extraction LM Reimann, Y Madhukumar Variyar, L Huelser, C Ghinami, D Germek, ... Philosophical Transactions A 383 (2288), 20230388, 2025 | 2 | 2025 |
| SoftFlow: automated hw-SW confidentiality verification for embedded processors LM Reimann, J Wiesner, D Sisejkovic, F Merchant, R Leupers 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration …, 2023 | 2 | 2023 |
| Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer R Pelke, J Cubero-Cascante, N Bosbach, N Degener, F Idrizi, ... arXiv preprint arXiv:2505.14303, 2025 | 1 | 2025 |
| Static Global Register Allocation for Dynamic Binary Translators N Zurstraβen, N Bosbach, LM Reimann, R Leupers 2025 Design, Automation & Test in Europe Conference (DATE), 1-6, 2025 | 1 | 2025 |
| Enhancing HW-SW Confidentiality Verification for Embedded Processors with SoftFlow’s Advanced Memory Range Feature LM Reimann, J Wiesner, K Jaszczyk, C Ghinami, D Germek, F Merchant, ... IFIP/IEEE International Conference on Very Large Scale Integration-System on …, 2023 | 1 | 2023 |
| Automated Information Flow Analysis for Integrated Computing-in-Memory Modules LM Reimann, F Staudigl, R Leupers 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 1-5, 2023 | 1 | 2023 |
| Integrity at Every Link: A Roadmap to Trustworthy Hardware Supply Chains LM Reimann, D Sisejkovic, R Leupers | 1 | |
| Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors E Rezunov, N Zurstraßen, LM Reimann, R Leupers arXiv preprint arXiv:2509.15782, 2025 | | 2025 |
Rainer LeupersRWTH AachenVerified email at ice.rwth-aachen.de
