| The 2021 magnonics roadmap A Barman, G Gubbiotti, S Ladak, AO Adeyeye, M Krawczyk, J Gräfe, ... Journal of Physics: Condensed Matter 33 (41), 413001, 2021 | 777 | 2021 |
| Advances in magnetics roadmap on spin-wave computing AV Chumak, P Kabos, M Wu, C Abert, C Adelmann, AO Adeyeye, ... IEEE Transactions on Magnetics 58 (6), 1-72, 2022 | 582 | 2022 |
| Introduction to spin wave computing A Mahmoud, F Ciubotaru, F Vanderveken, AV Chumak, S Hamdioui, ... Journal of Applied Physics 128 (16), 2020 | 424 | 2020 |
| A magnonic directional coupler for integrated magnonic half-adders Q Wang, M Kewenig, M Schneider, R Verba, F Kohl, B Heinz, M Geilen, ... Nature Electronics 3 (12), 765-774, 2020 | 289 | 2020 |
| A linear threshold gate implementation in single electron technology C Lageweg, S Cotofana, S Vassiliadis Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging …, 2001 | 151 | 2001 |
| The MOLEN ρμ-coded processor S Vassiliadis, S Wong, S Cotöfană International Conference on Field Programmable Logic and Applications, 275-285, 2001 | 146 | 2001 |
| Roadmap for unconventional computing with nanotechnology G Finocchio, JAC Incorvia, JS Friedman, Q Yang, A Giordano, J Grollier, ... Nano Futures 8 (1), 012001, 2024 | 109 | 2024 |
| A sum of absolute differences implementation in FPGA hardware S Wong, S Vassiliadis, S Cotofana Proceedings. 28th Euromicro Conference, 183-188, 2002 | 108 | 2002 |
| A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits Y Wang, S Cotofana, L Fang 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 175-180, 2011 | 96 | 2011 |
| Single electron encoded latches and flip-flops C Lageweg, S Cotofana, S Vassiliadis IEEE Transactions on Nanotechnology 3 (2), 237-248, 2004 | 88 | 2004 |
| Determining a coverage mask for a pixel D Crisu, S Cotofana, S Vassiliadis, P Liuha US Patent 7,006,110, 2006 | 87 | 2006 |
| Addition related arithmetic operations via controlled transport of charge S Cotofana, C Lageweg, S Vassiliadis IEEE Transactions on Computers 54 (3), 243-256, 2005 | 76 | 2005 |
| An O (n) residue number system to mixed radix conversion technique KA Gbolagade, SD Cotofana 2009 IEEE International Symposium on Circuits and Systems, 521-524, 2009 | 69 | 2009 |
| 2-1 addition and related arithmetic operations with threshold logic S Vassilladis, S Contofana, K Bertels Computers, IEEE Transactions on 45 (9), 1062-1067, 1996 | 61 | 1996 |
| Graphene nanoribbon based complementary logic gates and circuits Y Jiang, NC Laurenciu, H Wang, SD Cotofana IEEE Transactions on Nanotechnology 18, 287-298, 2019 | 54 | 2019 |
| Static buffered set based logic gates C Lageweg, S Cotofana, S Vassiliadis Proceedings of the 2nd IEEE Conference on Nanotechnology, 491-494, 2002 | 53 | 2002 |
| Field-programmable custom computing machines-a taxonomy M Sima, S Vassiliadis, S Cotofana, JTJ van Eijndhoven, K Vissers International Conference on Field Programmable Logic and Applications, 79-88, 2002 | 49 | 2002 |
| A full adder implementation using SET based linear threshold gates C Lageweg, S Cotofana, S Vassiliadis 9th International Conference on Electronics, Circuits and Systems 2, 665-668, 2002 | 48 | 2002 |
| Efficient computation reduction in Bayesian neural networks through feature decomposition and memorization X Jia, J Yang, R Liu, X Wang, SD Cotofana, W Zhao IEEE transactions on neural networks and learning systems 32 (4), 1703-1712, 2020 | 47 | 2020 |
| Memory-efficient dataflow inference for deep CNNs on FPGA L Petrica, T Alonso, M Kroes, N Fraser, S Cotofana, M Blott 2020 International Conference on Field-Programmable Technology (ICFPT), 48-55, 2020 | 46 | 2020 |
Florin CiubotaruImecVerified email at imec.be
