| FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface M Lee, W Tang, B Xue, J Wu, M Ma, Y Wang, Y Liu, D Fan, V Narayanan, ... Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2020 | 25 | 2020 |
| YOLoC: Deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip Y Chen, G Yin, Z Tan, M Lee, Z Yang, Y Liu, H Yang, K Ma, X Li Proceedings of the 59th ACM/IEEE Design Automation Conference, 1093-1098, 2022 | 24 | 2022 |
| Samba: Single-adc multi-bit accumulation compute-in-memory using nonlinearity-compensated fully parallel analog adder tree Y Chen, G Yin, M Zhou, W Tang, Z Yang, M Lee, X Du, J Yue, J Liu, ... IEEE Transactions on Circuits and Systems I: Regular Papers 70 (7), 2762-2773, 2023 | 23 | 2023 |
| Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm2 Density in 65-nm … G Yin, Y Chen, M Zhou, W Tang, M Lee, Z Yang, T Liao, X Du, ... IEEE Journal of Solid-State Circuits 59 (6), 1912-1925, 2023 | 19 | 2023 |
| Hidden-ROM: A compute-in-ROM architecture to deploy large-scale neural networks on chip with flexible and scalable post-fabrication task transfer capability Y Chen, G Yin, M Lee, W Tang, Z Yang, Y Liu, H Yang, X Li Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 14 | 2022 |
| A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM G Yin, Y Chen, M Lee, X Du, Y Ke, W Tang, Z Chen, M Zhou, J Yue, ... 2024 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2024 | 10 | 2024 |
| Victor: A variation-resilient approach using cell-clustered charge-domain computing for high-density high-throughput MLC CiM M Lee, W Tang, Y Chen, J Wu, H Zhong, Y Xu, Y Liu, H Yang, ... 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 10 | 2023 |
| FeFET-based logic-in-memory supporting SA-free write-back and fully dynamic access with reduced bitline charging activity and recycled bitline charge W Tang, M Lee, J Wu, Y Xu, Y Yu, Y Liu, K Ni, Y Wang, H Yang, ... IEEE Transactions on Circuits and Systems I: Regular Papers 70 (6), 2398-2411, 2023 | 8 | 2023 |
| FAST: A fully-concurrent access SRAM topology for high row-wise parallelism applications based on dynamic shift operations Y Chen, Y Fu, M Lee, S George, Y Liu, V Narayanan, H Yang, X Li IEEE Transactions on Circuits and Systems II: Express Briefs 70 (4), 1605-1609, 2022 | 5 | 2022 |
| Hybrid SRAM/ROM Compute-in-Memory Architecture for High Task-Level Energy Efficiency in Transformer Models With 8928-kb/mmTEXPRESERVE0 Density in 28nm CMOS G Yin, Y Chen, M Lee, X Du, Y Ke, W Tang, Z Chen, M Zhou, J Yue, ... IEEE Journal of Solid-State Circuits, 2025 | 3 | 2025 |
| A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface G Yin, M Zhou, Y Chen, W Tang, Z Yang, M Lee, X Du, J Yue, J Liu, ... arXiv preprint arXiv:2212.04320, 2022 | 3 | 2022 |
| Cross-Layer Design and Design Automation for In-Memory Computing based on Non-Volatile Memory Technologies XS Hu, MY Lee, M Li, JPC De Lima, L Liu, Z Zhu, J Castrillon, M Niemier, ... IEEE Design & Test, 2025 | 2 | 2025 |
| NeuroSim V1. 5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities J Read, MY Lee, WH Huang, YC Luo, A Lu, S Yu arXiv preprint arXiv:2505.02314, 2025 | 2 | 2025 |
| DCiROM: A Fully Digital Compute-in-ROM Design Approach to High Energy Efficiency of DNN Inference at Task Level T Yu, T Liao, M Zhou, X Chu, G Yin, M Lee, Y Liu, H Yang, X Li Proceedings of the 30th Asia and South Pacific Design Automation Conference …, 2025 | 2 | 2025 |
| CMOS+ X: Stacking Persistent Embedded Memories based on Oxide Transistors upon GPGPU Platforms F Waqar, MY Lee, S Yoon, S Lim, S Yu arXiv preprint arXiv:2506.23405, 2025 | 1 | 2025 |
| A 28nm 166.9 TOPS/W x Mb/mm2 DRAM-Free QLC Compute-in-ROM Macro Supporting High Task-Level Inference Energy Efficiency for Tiny AI Edge Devices LA Cheong, C Wang, M Zhou, T Liao, M Lee, Y Ke, W Tang, Y Chen, X Du, ... 2024 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2024 | 1 | 2024 |
| ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns Y Chen, G Yin, H Zhong, M Lee, H Yang, S George, V Narayanan, X Li 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 153-158, 2024 | 1 | 2024 |
| GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility Y Chen, M Lee, G Dai, M Zhou, N Challapalle, T Wang, Y Yu, Y Liu, ... IEEE Transactions on Emerging Topics in Computing 12 (1), 84-96, 2023 | 1 | 2023 |
| FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications Y Chen, Y Fu, M Lee, S George, Y Liu, V Narayanan, H Yang, X Li arXiv preprint arXiv:2205.11088, 2022 | 1 | 2022 |
| An NVM Non-Idealities Mitigation Solution Using Cell-Clustered Calibration for Analog High-Density Edge Multi-Level Cell Compute-in-Memory Z Xu, T Li, MY Lee, C Jia, S Zhang, S George, H Yang, V Narayanan, X Li IEEE Transactions on Circuits and Systems I: Regular Papers, 2025 | | 2025 |
