| TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs C Bolchini, A Miele, MD Santambrogio 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI …, 2007 | 222 | 2007 |
| Combined DVFS and mapping exploration for lifetime and soft-error susceptibility improvement in MPSoCs A Das, A Kumar, B Veeravalli, C Bolchini, A Miele 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 105 | 2014 |
| A novel design methodology for implementing reliability-aware systems on SRAM-based FPGAs C Bolchini, A Miele, C Sandionigi Computers, IEEE Transactions on 60 (12), 1744-1758, 2011 | 98 | 2011 |
| Reliability-driven system-level synthesis for mixed-critical embedded systems C Bolchini, A Miele IEEE Transactions on Computers 62 (12), 2489-2502, 2012 | 90 | 2012 |
| Floorplanning automation for partial-reconfigurable fpgas via feasible placements generation M Rabozzi, GC Durelli, A Miele, J Lillis, MD Santambrogio IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 151-164, 2016 | 72 | 2016 |
| Reliability-aware runtime power management for many-core systems in the dark silicon era AM Rahmani, MH Haghbayan, A Miele, P Liljeberg, A Jantsch, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (2), 427-440, 2016 | 69 | 2016 |
| A methodology for preference-based personalization of contextual data A Miele, E Quintarelli, L Tanca Proceedings of the 12th International Conference on Extending Database …, 2009 | 54 | 2009 |
| Run-time mapping for reliable many-cores based on energy/performance trade-offs C Bolchini, M Carminati, A Miele, A Das, A Kumar, B Veeravalli 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2013 | 52 | 2013 |
| Automated resource-aware floorplanning of reconfigurable areas in partially-reconfigurable FPGA systems C Bolchini, A Miele, C Sandionigi 2011 21st International Conference on Field Programmable Logic and …, 2011 | 50 | 2011 |
| Workload-aware power optimization strategy for asymmetric multiprocessors E Del Sozzo, GC Durelli, EMG Trainiti, A Miele, MD Santambrogio, ... 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 531-534, 2016 | 46 | 2016 |
| Fast and accurate error simulation for cnns against soft errors C Bolchini, L Cassano, A Miele, A Toschi IEEE Transactions on Computers 72 (4), 984-997, 2022 | 45 | 2022 |
| Self-adaptive fault tolerance in multi-/many-core systems C Bolchini, M Carminati, A Miele Journal of Electronic Testing 29 (2), 159-175, 2013 | 45 | 2013 |
| A lifetime-aware runtime mapping approach for many-core systems in the dark silicon era MH Haghbayan, A Miele, AM Rahmani, P Liljeberg, H Tenhunen 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 854-857, 2016 | 44 | 2016 |
| Performance/reliability-aware resource management for many-cores in dark silicon era MH Haghbayan, A Miele, AM Rahmani, P Liljeberg, H Tenhunen IEEE Transactions on Computers 66 (9), 1599-1612, 2017 | 40 | 2017 |
| Approximation-aware coordinated power/performance management for heterogeneous multi-cores A Kanduri, A Miele, AM Rahmani, P Liljeberg, C Bolchini, N Dutt Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 37 | 2018 |
| Fault models and injection strategies in SystemC specifications C Bolchini, A Miele, D Sciuto 2008 11th EUROMICRO Conference on Digital System Design Architectures …, 2008 | 37 | 2008 |
| An Adaptive Approach for Online Fault Management in Many-Core Architectures C Bolchini, A Miele, D Sciuto Design, Automation and Testing in Europe (DATE) Conference, 1429-1432, 2012 | 33 | 2012 |
| A lightweight and open-source framework for the lifetime estimation of multicore systems C Bolchini, M Carminati, M Gribaudo, A Miele 2014 IEEE 32nd International Conference on Computer Design (ICCD), 166-172, 2014 | 32 | 2014 |
| Hybrid service-oriented architectures: a case-study in the automotive domain L Baresi, C Ghezzi, A Miele, M Miraz, A Naggi, F Pacifici Proceedings of the 5th international workshop on software engineering and …, 2005 | 32 | 2005 |
| A model of soft error effects in generic IP processors C Bolchini, A Miele, F Salice, D Sciuto 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005 | 28 | 2005 |
