| Design and implementation of encryption/decryption architectures for BFV homomorphic encryption scheme AC Mert, E Öztürk, E Savaş IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (2), 353-362, 2019 | 148 | 2019 |
| A hardware accelerator for polynomial multiplication operation of CRYSTALS-KYBER PQC scheme F Yaman, AC Mert, E Öztürk, E Savaş 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 147 | 2021 |
| An extensive study of flexible design methods for the number theoretic transform AC Mert, E Karabulut, E Öztürk, E Savaş, A Aysu IEEE Transactions on Computers 71 (11), 2829-2843, 2020 | 132 | 2020 |
| KaLi : A Crystal for Post-Quantum Security Using Kyber and Dilithium A Aikata, AC Mert, M Imran, S Pagliarini, SS Roy IEEE Transactions on Circuits and Systems I: Regular Papers, 2022 | 106 | 2022 |
| Design and implementation of a fast and scalable NTT-based polynomial multiplier architecture AC Mert, E Öztürk, E Savaş 2019 22nd Euromicro Conference on Digital System Design (DSD), 253-260, 2019 | 103 | 2019 |
| Efficient number theoretic transform implementation on GPU for homomorphic encryption Ö Özerk, C Elgezen, AC Mert, E Öztürk, E Savaş The Journal of Supercomputing 78 (2), 2840-2872, 2022 | 98 | 2022 |
| A flexible and scalable NTT hardware: Applications from homomorphically encrypted deep learning to post-quantum cryptography AC Mert, E Karabulut, E Ozturk, E Savas, M Becchi, A Aysu 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020 | 76 | 2020 |
| High performance 2D transform hardware for future video coding AC Mert, E Kalali, I Hamzaoglu IEEE Transactions on Consumer Electronics 63 (2), 117-125, 2017 | 60 | 2017 |
| FPGA implementation of a run-time configurable NTT-based polynomial multiplication hardware AC Mert, E Öztürk, E Savaş Microprocessors and Microsystems 78, 103219, 2020 | 58 | 2020 |
| A computation and energy reduction technique for HEVC discrete cosine transform E Kalali, AC Mert, I Hamzaoglu IEEE Transactions on Consumer Electronics 62 (2), 166-174, 2016 | 57 | 2016 |
| CoHA-NTT: A configurable hardware accelerator for NTT-based polynomial multiplication K Derya, AC Mert, E Öztürk, E Savaş Microprocessors and Microsystems 89, 104451, 2022 | 56 | 2022 |
| Proteus: A pipelined ntt architecture generator F Hirner, AC Mert, SS Roy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 32 (7 …, 2024 | 47* | 2024 |
| Medha: Microcoded hardware accelerator for computing on encrypted data AC Mert, S Kwon, Y Shin, D Yoo, Y Lee, SS Roy arXiv preprint arXiv:2210.05476, 2022 | 47* | 2022 |
| A unified cryptoprocessor for lattice-based signature and key-exchange A Aikata, AC Mert, D Jacquemin, A Das, D Matthews, S Ghosh, SS Roy IEEE Transactions on Computers 72 (6), 1568-1580, 2022 | 41 | 2022 |
| REED: Chiplet-based accelerator for fully homomorphic encryption A Aikata, AC Mert, S Kwon, M Deryabin, SS Roy arXiv preprint arXiv:2308.02885, 2023 | 29 | 2023 |
| A low power versatile video coding (VVC) fractional interpolation hardware A CanMert, E Kalali, I Hamzaoglu 2018 Conference on Design and Architectures for Signal and Image Processing …, 2018 | 29 | 2018 |
| A reconfigurable fractional interpolation hardware for vvc motion compensation H Azgin, AC Mert, E Kalali, I Hamzaoglu 2018 21st Euromicro Conference on Digital System Design (DSD), 99-103, 2018 | 26 | 2018 |
| Low-latency asic algorithms of modular squaring of large integers for vdf evaluation AC Mert, E Öztürk, E Savaş IEEE Transactions on Computers 71 (1), 107-120, 2020 | 20 | 2020 |
| An efficient FPGA implementation of HEVC intra prediction H Azgin, AC Mert, E Kalali, I Hamzaoglu 2018 IEEE International Conference on Consumer Electronics (ICCE), 1-5, 2018 | 20 | 2018 |
| An FPGA implementation of future video coding 2D transform AC Mert, E Kalali, I Hamzaoglu 2017 IEEE 7th International Conference on Consumer Electronics-Berlin (ICCE …, 2017 | 18 | 2017 |
Sujoy Sinha RoyAssociate Professor, TU GrazVerified email at tugraz.at
