| Graph-based algorithms for boolean function manipulation RE Bryant Computers, IEEE Transactions on 100 (8), 677-691, 1986 | 13619 | 1986 |
| Symbolic boolean manipulation with ordered binary-decision diagrams RE Bryant ACM Computing Surveys (CSUR) 24 (3), 293-318, 1992 | 3353 | 1992 |
| Efficient implementation of a BDD package KS Brace, RL Rudell, RE Bryant ACM/IEEE Proc. 27th DAC, 40-45, 1990 | 1966* | 1990 |
| Semantics-aware malware detection M Christodorescu, S Jha, SA Seshia, D Song, RE Bryant 2005 IEEE symposium on security and privacy (S&P'05), 32-46, 2005 | 1199 | 2005 |
| Computer systems: a programmer's perspective R Bryant, DR O'Hallaron Prentice Hall, 2003 | 905 | 2003 |
| On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication RE Bryant IEEE transactions on Computers 40 (2), 205-213, 1991 | 803 | 1991 |
| Verification of arithmetic circuits with binary moment diagrams RE Bryant, YA Chen Design Automation, 1995. DAC'95. 32nd Conference on, 535-541, 1995 | 685 | 1995 |
| Simulation of packet communication architecture computer systems RE Bryant Massachusetts Institute of Technology, 1977 | 570 | 1977 |
| A switch-level model and simulator for MOS digital systems Bryant IEEE Transactions on computers 100 (2), 160-177, 1984 | 565 | 1984 |
| Formal verification by symbolic evaluation of partially-ordered trajectories CJH Seger, RE Bryant Formal Methods in System Design 6 (2), 147-189, 1995 | 402 | 1995 |
| Big-data computing: creating revolutionary breakthroughs in commerce, science and society R Bryant, RH Katz, ED Lazowska December, 2008 | 394 | 2008 |
| Binary decision diagrams and beyond: Enabling technologies for formal verification RE Bryant Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995 | 394 | 1995 |
| COSMOS: A Compiled Simulator for MOS Circuits RE Bryant, D Beatty, K Brace, K Cho, T Sheffler 24th ACM/IEEE Design Automation Conference, 9-16, 1987 | 387 | 1987 |
| Modeling and verifying systems using a logic of counter arithmetic with lambda expressions and uninterpreted functions RE Bryant, SK Lahiri, SA Seshia International Conference on Computer Aided Verification, 78-92, 2002 | 348 | 2002 |
| Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW MN Velev, RE Bryant Proceedings of the 38th annual design automation conference, 226-231, 2001 | 316 | 2001 |
| Boolean analysis of MOS circuits RE Bryant IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1987 | 279 | 1987 |
| Data-intensive supercomputing: The case for DISC RE Bryant technical report cmu-cs-07-128, carnegie mellon university, 2007 | 247 | 2007 |
| Symbolic manipulation of boolean functions using a graphical representation RE Bryant 22nd ACM/IEEE Design Automation Conference, 688-694, 1985 | 214 | 1985 |
| Deciding bit-vector arithmetic with abstraction RE Bryant, D Kroening, J Ouaknine, SA Seshia, O Strichman, B Brady International Conference on Tools and Algorithms for the Construction and …, 2007 | 206 | 2007 |
| Formally verifying a microprocessor using a simulation methodology DL Beatty, RE Bryant Proceedings of the 31st annual Design Automation Conference, 596-602, 1994 | 175 | 1994 |
Sanjit A. SeshiaProfessor of EECS, University of California, BerkeleyVerified email at eecs.berkeley.edu
