| Blasting through the Front-End Bottleneck with Shotgun R Kumar, B Grot, V Nagarajan Proceedings of the Twenty-Third International Conference on Architectural …, 2018 | 89 | 2018 |
| Boomerang: A Metadata-Free Architecture for Control Flow Delivery R Kumar, CC Huang, B Grot, V Nagarajan High Performance Computer Architecture (HPCA), 2017 IEEE International …, 2017 | 85 | 2017 |
| Twig: Profile-Guided BTB Prefetching for Data Center Applications TA Khan, N Brown, A Sriraman, N Soundararajan, R Kumar, J Devietti, ... 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021 | 54 | 2021 |
| Branch target buffer for a data processing apparatus R Kumar, B Grot, V Nagarajan, CC Huang | 35 | 2018 |
| Freeway: Maximizing MLP for Slice-Out-of-Order Execution R Kumar, M Alipour, D Black-Schaffer 2019 IEEE International Symposium on High Performance Computer Architecture …, 2019 | 34 | 2019 |
| C 3 D: Mitigating the NUMA bottleneck via coherent DRAM caches CC Huang, R Kumar, M Elver, B Grot, V Nagarajan Microarchitecture (MICRO), 2016 49th Annual IEEE/ACM International Symposium …, 2016 | 33 | 2016 |
| Delay and bypass: Ready and criticality aware instruction scheduling in out-of-order processors M Alipour, S Kaxiras, D Black-Schaffer, R Kumar 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020 | 26 | 2020 |
| Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment R Kumar, A Martínez, A González ACM Transactions on Architecture and Code Optimization (TACO) 11 (3), 25, 2014 | 23 | 2014 |
| Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources K Kanellopoulos, HC Nam, N Bostanci, R Bera, M Sadrosadati, R Kumar, ... Proceedings of the 56th Annual IEEE/ACM International Symposium on …, 2023 | 22 | 2023 |
| FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors M Alipour, R Kumar, S Kaxiras, D Black-Schaffer 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 716-721, 2019 | 21* | 2019 |
| Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings K Kanellopoulos, R Bera, K Stojiljkovic, FN Bostanci, C Firtina, ... Proceedings of the 56th Annual IEEE/ACM International Symposium on …, 2023 | 18 | 2023 |
| Dynamic selective devectorization for efficient power gating of SIMD units in a HW/SW co-designed environment R Kumar, A Martínez, A González Computer Architecture and High Performance Computing (SBAC-PAD), 2013 25th …, 2013 | 18 | 2013 |
| DARCO: Infrastructure for Research on HW/SW co-designed Virtual Machines D Pavlou, A Brankovic, R Kumar, M Gregori, K Stavrou, E Gibert, ... Proceedings of the 4th Workshop on Architectural and Microarchitectural …, 2011 | 18 | 2011 |
| A Storage-Effective BTB Organization for Servers T Asheim, B Grot, R Kumar 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 17 | 2023 |
| BTB-X: A Storage-Effective BTB Organization T Asheim, B Grot, R Kumar IEEE Computer Architecture Letters, 2021 | 16 | 2021 |
| Shooting Down the Server Front-End Bottleneck R Kumar, B Grot ACM Transactions on Computer Systems (TOCS) 38 (3-4), 1-30, 2022 | 10 | 2022 |
| Uncovering Hidden Instructions in Armv8-A Implementations F Strupe, R Kumar Workshop on Hardware and Architectural Support for Security and Privacy, 2020 | 9 | 2020 |
| Fetch-Directed Instruction Prefetching Revisited T Asheim, R Kumar, B Grot arXiv preprint arXiv:2006.13547, 2020 | 8 | 2020 |
| Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment R Kumar, A Martínez, A González ACM Transactions on Computer Systems (TOCS) 33 (4), 12, 2016 | 8 | 2016 |
| Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment R Kumar, A Martínez, A González High Performance Computing (HiPC), 2013 20th International Conference on, 79-88, 2013 | 8 | 2013 |
Boris GrotUniversity of EdinburghVerified email at ed.ac.uk
