| Security analysis of logic obfuscation J Rajendran, Y Pino, O Sinanoglu, R Karri Proceedings of the 49th annual design automation conference, 83-89, 2012 | 686 | 2012 |
| Fault analysis-based logic encryption J Rajendran, H Zhang, C Zhang, GS Rose, Y Pino, O Sinanoglu, R Karri IEEE Transactions on computers 64 (2), 410-424, 2013 | 595 | 2013 |
| Security analysis of integrated circuit camouflaging J Rajendran, M Sam, O Sinanoglu, R Karri Proceedings of the 2013 ACM SIGSAC conference on Computer & communications …, 2013 | 585 | 2013 |
| SARLock: SAT attack resistant logic locking M Yasin, B Mazumdar, JJV Rajendran, O Sinanoglu 2016 IEEE International Symposium on Hardware Oriented Security and Trust …, 2016 | 543 | 2016 |
| On improving the security of logic locking M Yasin, JJV Rajendran, O Sinanoglu, R Karri IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 474 | 2015 |
| Provably-secure logic locking: From theory to practice M Yasin, A Sengupta, MT Nabeel, M Ashraf, J Rajendran, O Sinanoglu Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications …, 2017 | 461 | 2017 |
| Removal attacks on logic locking and camouflaging techniques M Yasin, B Mazumdar, O Sinanoglu, J Rajendran IEEE Transactions on Emerging Topics in Computing 8 (2), 517-532, 2017 | 339 | 2017 |
| Is split manufacturing secure? J Rajendran, O Sinanoglu, R Karri 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 290 | 2013 |
| Security analysis of anti-sat M Yasin, B Mazumdar, O Sinanoglu, J Rajendran 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 342-347, 2017 | 214 | 2017 |
| Logic encryption: A fault analysis perspective J Rajendran, Y Pino, O Sinanoglu, R Karri 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 953-958, 2012 | 206 | 2012 |
| Sneak-path testing of crossbar-based nonvolatile random access memories S Kannan, J Rajendran, R Karri, O Sinanoglu IEEE Transactions on Nanotechnology 12 (3), 413-426, 2013 | 159 | 2013 |
| What to lock? Functional and parametric locking M Yasin, A Sengupta, BC Schafer, Y Makris, O Sinanoglu, J Rajendran Proceedings of the Great Lakes Symposium on VLSI 2017, 351-356, 2017 | 157 | 2017 |
| Keynote: A disquisition on logic locking A Chakraborty, NG Jayasankaran, Y Liu, J Rajendran, O Sinanoglu, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 153 | 2019 |
| Stripped functionality logic locking with hamming distance-based restore unit (SFLL-hd)–unlocked F Yang, M Tang, O Sinanoglu IEEE Transactions on Information Forensics and Security 14 (10), 2778-2786, 2019 | 138 | 2019 |
| CamoPerturb: Secure IC camouflaging for minterm protection M Yasin, B Mazumdar, O Sinanoglu, J Rajendran 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 126 | 2016 |
| Thwarting all logic locking attacks: Dishonest oracle with truly random logic locking N Limaye, E Kalligeros, N Karousos, IG Karybali, O Sinanoglu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 118 | 2020 |
| Regaining trust in VLSI design: Design-for-trust techniques J Rajendran, O Sinanoglu, R Karri Proceedings of the IEEE 102 (8), 1266-1282, 2014 | 114 | 2014 |
| Design and analysis of ring oscillator based design-for-trust technique J Rajendran, V Jyothi, O Sinanoglu, R Karri 29th VLSI Test Symposium, 105-110, 2011 | 114 | 2011 |
| GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists L Alrahis, A Sengupta, J Knechtel, S Patnaik, H Saleh, B Mohammad, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 110 | 2021 |
| Evolution of logic locking M Yasin, O Sinanoglu 2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017 | 105 | 2017 |
