| CORDIC architectures: A survey B Lakshmi, AS Dhar VLSI design 2010 (1), 794891, 2010 | 134 | 2010 |
| FPGA realization of a CORDIC based FFT processor for biomedical signal processing A Banerjee, AS Dhar, S Banerjee Microprocessors and Microsystems 25 (3), 131-142, 2001 | 97 | 2001 |
| A VLSI array architecture for realization of DFT, DHT, DCT and DST K Maharatna, AS Dhar, S Banerjee Signal Processing 81 (9), 1813-1822, 2001 | 75 | 2001 |
| An array architecture for fast computation of discrete Hartley transform AS Dhar, S Banerjee IEEE transactions on circuits and systems 38 (9), 1095-1098, 2002 | 71 | 2002 |
| CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis KC Ray, AS Dhar IEE Proceedings-Circuits, Devices and Systems 153 (6), 539-544, 2006 | 41 | 2006 |
| Real-time fault-tolerance with hot-standby topology for conditional sum adder A Mukherjee, AS Dhar Microelectronics Reliability 55 (3-4), 704-712, 2015 | 38 | 2015 |
| Architectural design and FPGA implementation of radix-4 CORDIC processor K Bhattacharyya, R Biswas, AS Dhar, S Banerjee Microprocessors and Microsystems 34 (2-4), 96-101, 2010 | 33 | 2010 |
| A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC M Chakraborty, AS Dhar, MH Lee IEEE Transactions on Circuits and Systems II: Express Briefs 52 (9), 530-534, 2005 | 30 | 2005 |
| Algorithm and VLSI architecture design of proportionate-type LMS adaptive filters for sparse system identification S Mula, VC Gogineni, AS Dhar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (9 …, 2018 | 29 | 2018 |
| Algorithm and architecture design of adaptive filters with error nonlinearities S Mula, VC Gogineni, AS Dhar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (9 …, 2017 | 29 | 2017 |
| VLSI architecture for parallel radix-4 CORDIC B Lakshmi, AS Dhar Microprocessors and Microsystems 37 (1), 79-86, 2013 | 25 | 2013 |
| VLSI architecture for low latency radix-4 CORDIC B Lakshmi, AS Dhar Computers & Electrical Engineering 37 (6), 1032-1042, 2011 | 23 | 2011 |
| Low-delay parallel architecture for fractal image compression M Panigrahy, I Chakrabarti, AS Dhar Circuits, Systems, and Signal Processing 35 (3), 897-917, 2016 | 22 | 2016 |
| CORDIC unit K Maharatna, E Grass, B Swapna, DA Sundar US Patent 7,606,852, 2009 | 21 | 2009 |
| FPGA implementation of discrete fractional Fourier transform M Prasad, KC Ray, AS Dhar 2010 International Conference on Signal Processing and Communications (SPCOM …, 2010 | 20 | 2010 |
| Efficient implementation of scan register insertion on integer arithmetic cores for FPGAs A Palchaudhuri, AS Dhar 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 18 | 2016 |
| Robust proportionate adaptive filter architectures under impulsive noise S Mula, VC Gogineni, AS Dhar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (5 …, 2019 | 16 | 2019 |
| A novel approach for fast and accurate mean error distance computation in approximate adders AS Roy, AS Dhar 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 16 | 2018 |
| Built-in fault localization circuitry for high performance FPGA based implementations A Palchaudhuri, AS Dhar Journal of Electronic Testing 33 (4), 529-537, 2017 | 16 | 2017 |
| A Novel -times Extended Coprime Array for DOA Estimation With Increased Degrees of Freedom RK Patra, AS Dhar IEEE Signal Processing Letters 29, 1402-1406, 2022 | 15 | 2022 |
Ayan PalchaudhuriIndian Institute of Technology BhubaneswarVerified email at iitbbs.ac.in
