| The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 494 | 2020 |
| A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives B Peccerillo, M Mannino, A Mondelli, S Bartolini Journal of Systems Architecture 129, 102561, 2022 | 146 | 2022 |
| Simulating a Multi-core x8664 Architecture with Hardware ISA Extension Supporting a Data-Flow Execution Model N Ho, A Portero, M Solinas, A Scionti, A Mondelli, P Faraboschi, R Giorgi 2014 2nd International Conference on Artificial Intelligence, Modelling and …, 2014 | 24 | 2014 |
| Enhancing an x86_64 multi-core architecture with data-flow execution support N Ho, A Mondelli, A Scionti, M Solinas, A Portero, R Giorgi Proceedings of the 12th ACM International Conference on Computing Frontiers, 1-2, 2015 | 21 | 2015 |
| The gem5 simulator: Version 20.0+. CoRR abs/2007.03152 (2020) J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 20 | 2020 |
| Dataflow support in x86_64 multicore architectures through small hardware extensions A Mondelli, N Ho, A Scionti, M Solinas, A Portero, R Giorgi 2015 Euromicro Conference on Digital System Design, 526-529, 2015 | 17 | 2015 |
| Revisiting clustered microarchitecture for future superscalar cores: A case for wide issue clusters P Michaud, A Mondelli, A Seznec ACM Transactions on Architecture and Code Optimization (TACO) 12 (3), 1-22, 2015 | 14 | 2015 |
| Supporting RISC-V full system simulation in gem5 PYH Hin, X Liao, J Cui, A Mondelli, TM Somu, N Zhang Proc. Workshop Comput. Architect. Res. RISC-V, 2021 | 10 | 2021 |
| IXIAM: ISA EXtension for integrated accelerator management B Peccerillo, E Cheshmikhani, M Mannino, A Mondelli, S Bartolini IEEE Access 11, 33768-33791, 2023 | 7 | 2023 |
| The gem5 simulator: Version 20.0+, 2020. DOI: 10.48550 J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... ARXIV, 2007 | 7 | 2007 |
| A general framework for accelerator management based on ISA extension E Cheshmikhani, B Peccerillo, A Mondelli, S Bartolini IEEE Access 10, 120702-120713, 2022 | 6 | 2022 |
| Revisiting wide superscalar microarchitecture A Mondelli Université de Rennes, 2017 | 5 | 2017 |
| Sempe: Secure multi path execution architecture for removing conditional branch side channels A Mondelli, P Gazzillo, Y Solihin 2021 58th ACM/IEEE Design Automation Conference (DAC), 973-978, 2021 | 2 | 2021 |
| An Architecture-Level CPU Modeling Framework for Power and Other Design Qualities Q Zhang, M Li, A Mondelli, Z Xie IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 1 | 2024 |
| Analysis and optimization of direct convolution execution on multi-core processors M Mannino, B Peccerillo, A Mondelli, S Bartolini IEEE Access 11, 57514-57528, 2023 | 1 | 2023 |
| Energy and Performance Improvements for Convolutional Accelerators Using Lightweight Address Translation Support M Mannino, B Peccerillo, A Mondelli, S Bartolini Proceedings of the 20th ACM International Conference on Computing Frontiers …, 2023 | 1 | 2023 |
| DeVAS: Decoupled Virtual Address Spaces M Mannino, B Peccerillo, A Mondelli, S Bartolini 2024 IEEE 36th International Symposium on Computer Architecture and High …, 2024 | | 2024 |
| Performance Considerations when Protecting Smart-City Devices from Side Channel Attacks A Mondelli, P Gazzillo, Y Solihin INTERNATIONAL CONFERENCE ON SMART TOURISM, SMART CITIES AND ENABLING …, 2019 | | 2019 |
| Performance consideration for protecting from side channel vulnerabilities A Mondelli, Y Solihin Arm Research Summit, 2019 | | 2019 |
| Characterizing the performance of inter-process sharing of persistent memory objects A Mondelli, Y Solihin Arm Research Summit, 2019 | | 2019 |
Biagio PeccerilloNational Research Council of Italy (CNR)Verified email at isti.cnr.it
