| Metis: An integrated morphing engine CPU to protect against side channel attacks F Antognazza, A Barenghi, G Pelosi IEEE Access 9, 69210-69225, 2021 | 15 | 2021 |
| A high efficiency hardware design for the post-quantum KEM HQC F Antognazza, A Barenghi, G Pelosi, R Susella 2024 IEEE International Symposium on Hardware Oriented Security and Trust …, 2024 | 12 | 2024 |
| A flexible ASIC-oriented design for a full NTRU accelerator F Antognazza, A Barenghi, G Pelosi, R Susella Proceedings of the 28th Asia and South Pacific Design Automation Conference …, 2023 | 11 | 2023 |
| An Efficient Unified Architecture for Polynomial Multiplications in Lattice-Based Cryptoschemes. F Antognazza, A Barenghi, G Pelosi, R Susella ICISSP, 81-88, 2023 | 7 | 2023 |
| Performance and efficiency exploration of hardware polynomial multipliers for post-quantum lattice-based cryptosystems F Antognazza, A Barenghi, G Pelosi, R Susella SN Computer Science 5 (2), 212, 2024 | 5 | 2024 |
| An Efficient and Unified RTL Accelerator Design for HQC-128, HQC-192, and HQC-256 F Antognazza, A Barenghi, G Pelosi IEEE Transactions on Computers, 2025 | 3 | 2025 |
| High-Performance FPGA Accelerator for the Post-quantum Signature Scheme CROSS P Karl, F Antognazza, A Barenghi, G Pelosi, G Sigl Cryptology ePrint Archive, 2025 | 3 | 2025 |
| A Versatile and Unified HQC Hardware Accelerator F Antognazza, A Barenghi, G Pelosi, R Susella International Conference on Applied Cryptography and Network Security, 214-219, 2024 | 2 | 2024 |
| Hardware design and implementation of post-quantum cryptographic algorithms: The case of NTRU, HQC and CROSS F Antognazza MS thesis, Politecnico di Milano, 2025 | 1 | 2025 |
| Hardware Design and Implementation of Post-quantum Cryptographic Algorithms F Antognazza | | 2025 |
| Countering side channel attacks in an in-order RISC-V processor with a code morphing based execution mode F Antognazza Politecnico di Milano, 2019 | | 2019 |
