| Exploring potential benefits of 3D FPGA integration C Ababei, P Maidee, K Bazargan International Conference on Field Programmable Logic and Applications, 874-880, 2004 | 319 | 2004 |
| Timing-driven partitioning-based placement for island style FPGAs P Maidee, C Ababei, K Bazargan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 113 | 2005 |
| Fast timing-driven partitioning-based placement for island style FPGAs P Maidee, C Ababei, K Bazargan Proceedings of the 40th annual design automation conference, 598-603, 2003 | 91 | 2003 |
| RapidStream: Parallel physical implementation of FPGA HLS designs L Guo, P Maidee, Y Zhou, C Lavin, J Wang, Y Chi, W Qiao, A Kaviani, ... Proceedings of the 2022 ACM/SIGDA International Symposium on Field …, 2022 | 58 | 2022 |
| RWRoute: An open-source timing-driven router for commercial FPGAs Y Zhou, P Maidee, C Lavin, A Kaviani, D Stroobandt ACM Transactions on Reconfigurable Technology and Systems (TRETS) 15 (1), 1-27, 2021 | 33 | 2021 |
| Yuze Chi L Guo, P Maidee, Y Zhou, C Lavin, J Wang Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang …, 2023 | 21 | 2023 |
| An open-source lightweight timing model for RapidWright P Maidee, C Neely, A Kaviani, C Lavin 2019 International Conference on Field-Programmable Technology (ICFPT), 171-178, 2019 | 17 | 2019 |
| LinkBlaze: Efficient global data movement for FPGAs P Maidee, A Kaviani, K Zeng 2017 International Conference on ReConFigurable Computing and FPGAs …, 2017 | 11 | 2017 |
| Active-by-active programmable device AS Kaviani, P Maidee, I Bolsens US Patent 10,002,100, 2018 | 10 | 2018 |
| Rapidstream 2.0: Automated parallel implementation of latency–insensitive fpga designs through partial reconfiguration L Guo, P Maidee, Y Zhou, C Lavin, E Hung, W Li, J Lau, W Qiao, Y Chi, ... ACM Transactions on Reconfigurable Technology and Systems 16 (4), 1-30, 2023 | 9 | 2023 |
| Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, and Jason Cong. 2023. RapidStream 2.0: Automated Parallel Implementation of Latency Insensitive FPGA … L Guo, P Maidee, Y Zhou, C Lavin, E Hung, W Li, J Lau, W Qiao ACM Trans. Reconfigurable Technol. Syst 16 (4), 2023 | 9 | 2023 |
| System-level interconnect ring for a programmable integrated circuit AS Kaviani, P Maidee, EF Dellinger US Patent 10,042,806, 2018 | 9 | 2018 |
| Multiplexer-based ternary content addressable memory P Maidee US Patent 9,653,165, 2017 | 9 | 2017 |
| Defect-tolerant FPGA architecture exploration P Maidee, K Bazargan 2006 International Conference on Field Programmable Logic and Applications, 1-6, 2006 | 9 | 2006 |
| Packet-based and time-multiplexed network-on-chip Z Blair, P Maidee, AS Kaviani US Patent 11,496,418, 2022 | 6 | 2022 |
| Improving FPGA NoC performance using virtual cut-through switching technique P Maidee, A Kaviani 2015 International Conference on ReConFigurable Computing and FPGAs …, 2015 | 4 | 2015 |
| Pipelined data channel with ready/valid handshaking P Maidee US Patent 10,515,047, 2019 | 3 | 2019 |
| A fast SPFD-based rewiring technique P Maidee, K Bazargan 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 55-60, 2010 | 2 | 2010 |
| FPGA family composition and effects of specialized blocks P Maidee, N Hakim, K Bazargan 2008 International Conference on Field Programmable Logic and Applications …, 2008 | 2 | 2008 |
| A generalized and unified SPFD-based rewiring technique P Maidee, K Bazargan 2007 International Conference on Field Programmable Logic and Applications …, 2007 | 2 | 2007 |
