| Source-based delay-bounded multicasting in multimedia networks CP Ravikumar, R Bajpai Computer communications 21 (2), 126-132, 1998 | 137 | 1998 |
| At-speed transition fault testing with low speed scan enable N Ahmed, CP Ravikumar, M Tehranipoor, J Plusquellic 23rd IEEE VLSI Test Symposium (VTS'05), 42-47, 2005 | 84 | 2005 |
| Test strategies for low power devices CP Ravikumar, M Hirech, X Wen Proceedings of the conference on Design, automation and test in Europe, 728-733, 2008 | 64 | 2008 |
| Partial gating optimization for power reduction during test application M ElShoukry, M Tehranipoor, CP Ravikumar 14th Asian Test Symposium (ATS'05), 242-247, 2005 | 58 | 2005 |
| Leakage power estimation for deep submicron circuits in an ASIC design environment R Kumar, CP Ravikumar Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design …, 2002 | 56 | 2002 |
| Glitch-aware pattern generation and optimization framework for power-safe scan test VR Devanathan, CP Ravikumar, V Kamakoti 25th IEEE VLSI Test Symposium (VTS'07), 167-172, 2007 | 53 | 2007 |
| Software power optimizations in an embedded system V Dalal, CP Ravikumar VLSI Design 2001. Fourteenth International Conference on VLSI Design, 254-259, 2001 | 53 | 2001 |
| Local at-speed scan enable generation for transition fault testing using low-cost testers N Ahmed, M Tehranipoor, CP Ravikumar, KM Butler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 50 | 2007 |
| Genetic algorithm for mapping tasks onto a reconfigurable parallel processor CP Ravikumar, AK Gupta IEE Proceedings-Computers and Digital Techniques 142 (2), 81-86, 1995 | 46 | 1995 |
| Simultaneous module selection and scheduling for power-constrained testing of core based systems CP Ravikumar, G Chandra, A Verma VLSI Design 2000. Wireless and Digital Imaging in the Millennium …, 2000 | 39 | 2000 |
| A polynomial-time algorithm for power constrained testing of core based systems CP Ravikumar, A Verma, G Chandra Proceedings Eighth Asian Test Symposium (ATS'99), 107-112, 1999 | 39 | 1999 |
| Enhanced launch-off-capture transition fault testing N Ahmed, M Tehranipoor, CP Ravikumar IEEE International Conference on Test, 2005., 10 pp.-255, 2005 | 38 | 2005 |
| A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test VR Devanathan, CP Ravikumar, V Kamakoti 2007 IEEE International Test Conference, 1-10, 2007 | 36 | 2007 |
| Fast, layout-aware validation of test-vectors for nanometer-related timing failures A Kokrady, CP Ravikumar 17th International Conference on VLSI Design. Proceedings., 597-602, 2004 | 36 | 2004 |
| PMScan: A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test VR Devanathan, CP Ravikumar, R Mehrotra, V Kamakoti 2007 IEEE International Test Conference, 1-9, 2007 | 33 | 2007 |
| On power-profiling and pattern generation for power-safe scan tests VR Devanathan, CP Ravikumar, V Kamakoti 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 32 | 2007 |
| Multiprocessor architectures for embedded system-on-chip applications CP Ravikumar 17th International Conference on VLSI Design. Proceedings., 512-519, 2004 | 32 | 2004 |
| Static verification of test vectors for IR drop failure AA Kokrady, CP Ravikumar ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 31 | 2003 |
| A survey of association rule mining using genetic algorithm A Sharma, N Tivari International Journal of Computer Applications & Information Technology 1 (2 …, 2012 | 30 | 2012 |
| A critical-path-aware partial gating approach for test power reduction M Elshoukry, M Tehranipoor, CP Ravikumar ACM Transactions on Design Automation of Electronic Systems (TODAES) 12 (2 …, 2007 | 29 | 2007 |
Devanathan VaradarajanTexas Instruments Inc.Verified email at ti.com
