| Advanced BDD optimization R Ebendt, G Fey, R Drechsler Springer US, 2005 | 136 | 2005 |
| On acceleration of SAT-based ATPG for industrial designs R Drechsler, S Eggergluss, G Fey, A Glowatz, F Hapke, J Schloeffel, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 130 | 2008 |
| Automatic fault localization for property checking G Fey, S Staber, R Bloem, R Drechsler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 110 | 2008 |
| Synthesis of fully testable circuits from BDDs R Drechsler, J Shi, G Fey IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 98 | 2004 |
| Using unsatisfiable cores to debug multiple design errors A Sülflow, G Fey, R Bloem, R Drechsler Proceedings of the 18th ACM Great Lakes symposium on VLSI, 77-82, 2008 | 94 | 2008 |
| PASSAT: Efficient SAT-based test pattern generation for industrial circuits J Shi, G Fey, R Drechsler, A Glowatz, F Hapke, J Schloffel IEEE computer society annual symposium on VLSI: new frontiers in VLSI Design …, 2005 | 77 | 2005 |
| Test pattern generation using Boolean proof engines R Drechsler, S Eggersglüβ, G Fey, D Tille Springer Netherlands, 2009 | 70 | 2009 |
| SWORD: A SAT like prover using word level information R Wille, G Fey, D Große, D Große, S Eggersglüß, R Drechsler VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended …, 2009 | 70 | 2009 |
| Automatic generation of complex properties for hardware designs F Rogin, T Klotz, G Fey, R Drechsler, S Rülke Proceedings of the conference on Design, automation and test in Europe, 545-548, 2008 | 70 | 2008 |
| ParSyC: an efficient SystemC parser G Fey, D Große, T Cassens, C Genz, T Warode, R Drechsler Workshop on Synthesis And System Integration of Mixed Information …, 2004 | 54 | 2004 |
| OBC-NG: Towards a reconfigurable on-board computing architecture for spacecraft D Lüdtke, K Westerdorff, K Stohlmann, A Börner, O Maibaum, T Peng, ... 2014 IEEE Aerospace Conference, 1-13, 2014 | 53 | 2014 |
| Minimizing the number of paths in BDDs: Theory and algorithm G Fey, R Drechsler IEEE Transactions on Computer-Aided Design of Integrated circuits and …, 2005 | 50 | 2005 |
| A basis for formal robustness checking G Fey, R Drechsler 9th International Symposium on Quality Electronic Design (isqed 2008), 784-789, 2008 | 49 | 2008 |
| Effective robustness analysis using bounded model checking techniques G Fey, A Sulflow, S Frehse, R Drechsler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 48 | 2011 |
| WoLFram-a word level framework for formal verification A Sülflow, U Kühne, G Fey, D Grosse, R Drechsler 2009 IEEE/IFIP International Symposium on Rapid System Prototyping, 11-17, 2009 | 46 | 2009 |
| Project-based learning in student teams in computer science education A Breiter, G Fey, R Drechsler Facta universitatis-series: Electronics and Energetics 18 (2), 165-180, 2005 | 44 | 2005 |
| Cost-efficient block verification for a UMTS up-link chip-rate coprocessor K Winkelmann, HJ Trylus, D Stoffel, G Fey Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 43 | 2004 |
| metaSMT: Focus on your application not on solver integration F Haedicke, S Frehse, G Fey, D Große, R Drechsler International Workshop on Design and Implementation of Formal Tools and …, 2011 | 40 | 2011 |
| Computing bounds for fault tolerance using formal techniques G Fey, A Sülflow, R Drechsler Proceedings of the 46th Annual Design Automation Conference, 190-195, 2009 | 37 | 2009 |
| SyCE: An integrated environment for system design in SystemC R Drechsler, G Fey, C Genz, D Große 16th IEEE International Workshop on Rapid System Prototyping (RSP'05), 258-260, 2005 | 37 | 2005 |
