| 16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications YD Chih, PH Lee, H Fujiwara, YC Shih, CF Lee, R Naous, YL Chen, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 252-254, 2021 | 436 | 2021 |
| A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous … H Fujiwara, H Mori, WC Zhao, MC Chuang, R Naous, CK Chuang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 235 | 2022 |
| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 207 | 2016 |
| Design considerations for complementary nanoelectromechanical logic gates K Akarvardar, D Elata, R Parsa, GC Wan, K Yoo, J Provine, P Peumans, ... 2007 IEEE International Electron Devices Meeting, 299-302, 2007 | 204 | 2007 |
| A 7-nm compute-in-memory SRAM macro supporting multi-bit input, weight and output and achieving 351 TOPS/W and 372.4 GOPS ME Sinangil, B Erbagci, R Naous, K Akarvardar, D Sun, WS Khwa, ... IEEE Journal of Solid-State Circuits 56 (1), 188-198, 2020 | 188 | 2020 |
| A 4nm 6163-TOPS/W/b SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight … H Mori, WC Zhao, CE Lee, CF Lee, YH Hsu, CK Chuang, T Hashizume, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 132-134, 2023 | 115 | 2023 |
| Efficient FPGAs using nanoelectromechanical relays C Chen, R Parsa, N Patil, S Chong, K Akarvardar, J Provine, D Lewis, ... Proceedings of the 18th annual ACM/SIGDA international symposium on Field …, 2010 | 114 | 2010 |
| Analytical modeling of the suspended-gate FET and design insights for low-power logic K Akarvardar, C Eggimann, D Tsamados, YS Chauhan, GC Wan, ... IEEE transactions on Electron Devices 55 (1), 48-59, 2007 | 111 | 2007 |
| Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage S Chong, K Akarvardar, R Parsa, JB Yoon, RT Howe, S Mitra, HSP Wong Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 99 | 2009 |
| Method for dual-channel nanowire FET device CC Hobbs, K Akarvardar US Patent 8,183,104, 2012 | 86 | 2012 |
| A density metric for semiconductor technology [point of view] HSP Wong, K Akarvardar, D Antoniadis, J Bokor, C Hu, TJ King-Liu, ... Proceedings of the IEEE 108 (4), 478-482, 2020 | 80 | 2020 |
| FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 79 | 2016 |
| Investigation of the four-gate action in G/sup 4/-FETs B Dufrene, K Akarvardar, S Cristoloveanu, BJ Blalock, R Gentil, E Kolawa, ... IEEE transactions on electron devices 51 (11), 1931-1935, 2004 | 76 | 2004 |
| Methods of forming FinFET devices with alternative channel materials WP Maszara, AP Jacob, NV LiCausi, JA FRONHEISER, K Akarvardar US Patent 8,673,718, 2014 | 69 | 2014 |
| PCM-based analog compute-in-memory: Impact of device non-idealities on inference accuracy X Sun, WS Khwa, YS Chen, CH Lee, HY Lee, SM Yu, R Naous, JY Wu, ... IEEE Transactions on Electron Devices 68 (11), 5585-5591, 2021 | 62 | 2021 |
| Low-frequency noise in SOI four-gate transistors K Akarvardar, BM Dufrene, S Cristoloveanu, P Gentil, BJ Blalock, ... IEEE transactions on electron devices 53 (4), 829-835, 2006 | 62 | 2006 |
| Strained SiGe and Si FinFETs for high performance logic with SiGe/Si stack on SOI I Ok, K Akarvardar, S Lin, M Baykan, CD Young, PY Hung, MP Rodgers, ... 2010 International Electron Devices Meeting, 34.2. 1-34.2. 4, 2010 | 61 | 2010 |
| Analytical modeling of the two-dimensional potential distribution and threshold voltage of the SOI four-gate transistor K Akarvardar, S Cristoloveanu, P Gentil IEEE Transactions on Electron Devices 53 (10), 2569-2577, 2006 | 61 | 2006 |
| 34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture … H Fujiwara, H Mori, WC Zhao, K Khare, CE Lee, X Peng, V Joshi, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 572-574, 2024 | 56 | 2024 |
| Ultralow voltage crossbar nonvolatile memory based on energy-reversible NEM switches K Akarvardar, HSP Wong IEEE Electron Device Letters 30 (6), 626-628, 2009 | 56 | 2009 |
