| INDEP approach for leakage reduction in nanoscale CMOS circuits VK Sharma, M Pattanaik, B Raj International Journal of Electronics 102 (2), 200-215, 2015 | 140 | 2015 |
| ONOFIC approach: low power high speed nanoscale VLSI circuits design VK Sharma, M Pattanaik, B Raj International Journal of Electronics 101 (1), 61-73, 2014 | 136 | 2014 |
| Clock gating based energy efficient ALU design and implementation on FPGA B Pandey, J Yadav, M Pattanaik, N Rajoria 2013 International Conference on energy efficient technologies for …, 2013 | 117 | 2013 |
| PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits VK Sharma, M Pattanaik, B Raj Microelectronics reliability 54 (1), 90-99, 2014 | 113 | 2014 |
| Forward body biased multimode multi-threshold CMOS technique for ground bounce noise reduction in static CMOS adders S Sharma, A Kumar, M Pattanaik, B Raj International Journal of Information and Electronics Engineering 3 (3), 567-572, 2013 | 95 | 2013 |
| Diode based trimode multi-threshold CMOS technique for ground bounce noise reduction in static CMOS adders M Pattanaik, B Raj, S Sharma, A Kumar Advanced materials research 548, 885-889, 2012 | 88 | 2012 |
| Leakage current ONOFIC approach for deep submicron VLSI circuit design VK Sharma, M Pattanaik, B Raj International Journal of Electrical, Computer, Electronics and Communication …, 2013 | 83 | 2013 |
| Static noise margin analysis of various SRAM topologies S Birla, RK Singh, M Pattnaik International Journal of Engineering and Technology 3 (3), 304, 2011 | 74 | 2011 |
| Device and circuit design challenges for low leakage SRAM for ultra low power applications S Birla, NK Shukla, M Pattanaik, RK Singh Canadian Journal on Electrical & Electronics Engineering 1 (7), 156-167, 2010 | 52 | 2010 |
| Implementation of Boolean and arithmetic functions with 8T SRAM cell for in-memory computation AK Rajput, M Pattanaik 2020 International Conference for Emerging Technology (INCET), 1-5, 2020 | 49 | 2020 |
| Histogram statistics based variance controlled adaptive threshold in anisotropic diffusion for low contrast image enhancement KV Arya, M Pattanaik Signal Processing 93 (6), 1684-1693, 2013 | 49 | 2013 |
| Simulation study of hetero dielectric tri material gate tunnel FET based common source amplifier circuit U Dutta, MK Soni, M Pattanaik AEU-International Journal of Electronics and Communications 99, 258-263, 2019 | 47 | 2019 |
| Clock gating aware low power ALU design and implementation on FPGA B Pandey, M Pattanaik International Journal of Future Computer and Communication 2 (5), 461, 2013 | 47 | 2013 |
| Design of low leakage variability aware ONOFIC CMOS standard cell library VK Sharma, M Pattanaik Journal of Circuits, Systems and Computers 25 (11), 1650134, 2016 | 44 | 2016 |
| Advancement in Nanoscale CMOS Device Design En Route to Ultra‐Low‐Power Applications S Dhar, M Pattanaik, P Rajaram VLSI Design 2011 (1), 178516, 2011 | 44 | 2011 |
| A reliable ground bounce noise reduction technique for nanoscale CMOS circuits VK Sharma, M Pattanaik International Journal of Electronics 102 (11), 1852-1866, 2015 | 43 | 2015 |
| Techniques for low leakage nanoscale VLSI circuits: A comparative study VK Sharma, M Pattanaik Journal of Circuits, Systems, and Computers 23 (05), 1450061, 2014 | 43 | 2014 |
| VLSI scaling methods and low power CMOS buffer circuit VK Sharma, M Pattanaik Journal of Semiconductors 34 (9), 095001, 2013 | 42 | 2013 |
| Clock gated low power sequential circuit design MP Dev, D Baghel, B Pandey, M Pattanaik, A Shukla 2013 IEEE Conference on Information & Communication Technologies, 440-444, 2013 | 42 | 2013 |
| High performance process variations aware technique for sub-threshold 8T-SRAM cell VK Sharma, S Patel, M Pattanaik Wireless personal communications 78 (1), 57-68, 2014 | 41 | 2014 |
