| Metal gate structures and methods for forming thereof S Ganguli, SH Yu, SH Lee, HC Ha, WT Lee, H Kim, S Gandikota, Y Lei, ... US Patent 8,637,390, 2014 | 517 | 2014 |
| NMOS metal gate materials, manufacturing methods, and equipment using CVD and ALD processes with metal based precursors S Ganguli, S Gandikota, Y Lei, X Lu, SH Yu, H Kim, PF Ma, M Chang, ... US Patent 8,642,468, 2014 | 435 | 2014 |
| Replacement metal gate and fabrication process with reduced lithography steps MG Sung, C Park, H Kim US Patent 10,176,996, 2019 | 430 | 2019 |
| Common fabrication of different semiconductor devices with different threshold voltages H Kim, K Choi, JY Lee US Patent App. 14/134,358, 2015 | 421 | 2015 |
| Semiconductor gate structure for threshold voltage modulation and method of making same H Kim, K Choi US Patent 8,932,923, 2015 | 419 | 2015 |
| Cu wettability and diffusion barrier property of Ru thin film for Cu metallization H Kim, T Koseki, T Ohba, T Ohta, Y Kojima, H Sato, Y Shimogaki Journal of The Electrochemical Society 152 (8), G594, 2005 | 165 | 2005 |
| Mechanism of Co liner as enhancement layer for Cu interconnect gap-fill M He, X Zhang, T Nogami, X Lin, J Kelly, H Kim, T Spooner, D Edelstein, ... Journal of The Electrochemical Society 160 (12), D3040, 2013 | 135 | 2013 |
| Methods of forming gate structures with multiple work functions and the resulting products K Choi, H Kim US Patent 9,012,319, 2015 | 117 | 2015 |
| A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI KI Seo, B Haran, D Gupta, D Guo, T Standaert, R Xie, H Shang, E Alptekin, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 112 | 2014 |
| Selective chemical vapor deposition of manganese self-aligned capping layer for Cu interconnections in microelectronics Y Au, Y Lin, H Kim, E Beh, Y Liu, RG Gordon Journal of The Electrochemical Society 157 (6), D341, 2010 | 103 | 2010 |
| Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance SH Lee, SH Yu, WT Lee, S Ganguli, HC Ha, H Kim US Patent 9,129,945, 2015 | 99 | 2015 |
| Cobalt nitride layers for copper interconnects and methods for forming them RG Gordon, H Kim, H BHANDARI US Patent 7,973,189, 2011 | 82 | 2011 |
| Self-aligned wrap-around contacts for nanosheet devices R Xie, C Park, MG Sung, H Kim US Patent 9,847,390, 2017 | 62 | 2017 |
| Integrated circuit and method for fabricating the same having a replacement gate structure K Choi, H Kim US Patent 8,987,126, 2015 | 54 | 2015 |
| Atomic layer deposition of Ru thin films using a Ru (0) metallorganic precursor and O2 TE Hong, SH Choi, S Yeo, JY Park, SH Kim, T Cheon, H Kim, MK Kim, ... ECS Journal of Solid State Science and Technology 2 (3), P47, 2012 | 54 | 2012 |
| Semiconductor device with a gate contact positioned above the active region R Xie, C Park, MG Sung, H Kim US Patent 9,735,242, 2017 | 53 | 2017 |
| Self-aligned barrier layers for interconnects RG Gordon, H Kim US Patent 7,932,176, 2011 | 52 | 2011 |
| Method and structure of forming self-aligned RMG gate for VFET R Xie, C Park, MG Sung, H Kim US Patent 9,780,208, 2017 | 49 | 2017 |
| Material consideration on Ta, Mo, Ru, and Os as glue layer for ultra large scale integration Cu interconnects H Kim, Y Naito, T Koseki, T Ohba, T Ohta, Y Kojima, H Sato, Y Shimogaki Japanese journal of applied physics 45 (4R), 2497, 2006 | 46 | 2006 |
| Semiconductor devices with copper interconnects and methods for fabricating same X Zhang, H Kim US Patent 9,190,323, 2015 | 44 | 2015 |
Min Gyu SungIBMVerified email at ibm.com
