| Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing B Tang, H Veluri, Y Li, ZG Yu, M Waqar, JF Leong, M Sivan, E Zamburg, ... Nature Communications 13 (1), 3037, 2022 | 235 | 2022 |
| All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration M Sivan, Y Li, H Veluri, Y Zhao, B Tang, X Wang, E Zamburg, JF Leong, ... Nature communications 10 (1), 5201, 2019 | 215 | 2019 |
| Low Subthreshold Swing and High Mobility Amorphous Indium–Gallium–Zinc-Oxide Thin-Film Transistor With Thin HfO2 Gate Dielectric and Excellent Uniformity S Samanta, U Chand, S Xu, K Han, Y Wu, C Wang, A Kumar, H Velluri, ... IEEE Electron Device Letters 41 (6), 856-859, 2020 | 91 | 2020 |
| High-throughput, area-efficient, and variation-tolerant 3-D in-memory compute system for deep convolutional neural networks H Veluri, Y Li, JX Niu, E Zamburg, AVY Thean IEEE Internet of Things Journal 8 (11), 9219-9232, 2021 | 25 | 2021 |
| 2-kbit Array of 3-D Monolithically-stacked IGZO FETs with Low SS-64mV/dec, Ultra-low-leakage, Competitive μ-57 cm2/V-s Performance and Novel nMOS-Only … U Chand, Z Fang, C Chun-Kuei, Y Luo, H Veluri, M Sivan, LJ Feng, ... 2021 Symposium on VLSI Technology, 1-2, 2021 | 23 | 2021 |
| Low-thermal-budget BEOL-compatible beyond-silicon transistor technologies for future monolithic-3D compute and memory applications A Thean, SH Tsai, CK Chen, M Sivan, B Tang, S Hooda, Z Fang, J Pan, ... 2022 International Electron Devices Meeting (IEDM), 12.2. 1-12.2. 4, 2022 | 20 | 2022 |
| Aerosol Jet Printed WSe2 Based RRAM on Kapton Suitable for Flexible Monolithic Memory Integration Y Li, M Sivan, JX Niu, H Veluri, E Zamburg, J Leong, U Chand, S Samanta, ... 2019 IEEE international conference on flexible and printable sensors and …, 2019 | 13 | 2019 |
| Sub-10nm Ultra-thin ZnO Channel FET with Record-High 561 µA/µm ION at VDS 1V, High µ-84 cm2/V-s and1T-1RRAM Memory Cell Demonstration Memory … U Chand, MMS Aly, M Lal, C Chun-Kuei, S Hooda, SH Tsai, Z Fang, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 12 | 2022 |
| Quantifying the benefits of monolithic 3D computing systems enabled by TFT and RRAM AM Felfel, K Datta, A Dutt, H Veluri, A Zaky, AVY Thean, MMS Aly 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 43-48, 2020 | 11 | 2020 |
| A low-power DNN accelerator enabled by a novel staircase RRAM array H Veluri, U Chand, Y Li, B Tang, AVY Thean IEEE Transactions on Neural Networks and Learning Systems 34 (8), 4416-4427, 2021 | 10 | 2021 |
| A low-latency DNN accelerator enabled by DFT-based convolution execution within crossbar arrays H Veluri, U Chand, CK Chen, AVY Thean IEEE Transactions on Neural Networks and Learning Systems, 2023 | 8 | 2023 |
| Waferscale solution-processed 2D material analog resistive memory array for memory-based computing. Nat. Commun. 13, 3037 B Tang, H Veluri, Y Li, ZG Yu, M Waqar, JF Leong, M Sivan, E Zamburg, ... | 5 | 2022 |
| BMX-FPCA: 3D Beyond-Moore Flexible Field Programmable Crossbar Array Architecture H Veluri, D Vasudevan 2024 25th International Symposium on Quality Electronic Design (ISQED), 1-9, 2024 | 2 | 2024 |
| Extremely- Scaled Channel Thickness ZnO FET with High Mobility 86 cm2/V-s, Low SS of 83mV/dec and Low Thermal Budget Process (<300°C) U Chand, C Chun-Kuei, M Lal, S Hooda, H Veluri, Z Fang, SH Tsai, ... 2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM …, 2022 | 2 | 2022 |
| Design-Technology Co-optimization (DTCO) for Emerging Disruptive Logic & Embedded Memory Process Technologies JX Niu, H Veluri, AVY Thean 2019 Electron Devices Technology and Manufacturing Conference (EDTM), 246-248, 2019 | 2 | 2019 |
| Design of Artificial Spiking Neuron with SiO2 Memristive Synapse to Demonstrate Neuron-Level Spike Timing Dependent Plasticity JX Niu, H Veluri, Y Li, U Chand, JF Leong, E Zamburg, M Sivan, ... 2019 International Conference on IC Design and Technology (ICICDT), 1-3, 2019 | 1 | 2019 |
| InFormer: A High-throughput, Ultra-efficient In-memory Compute-based Floating-point Arithmetic Accelerator for Transformers H Veluri, D Vasudevan Proceedings of the Great Lakes Symposium on VLSI 2025, 718-725, 2025 | | 2025 |
| An Error-Resilient Compute-in-Memory 3D FPCA Architecture for High-Performance Floating-Point Operations H Veluri, D Vasudevan 2025 26th International Symposium on Quality Electronic Design (ISQED), 1-9, 2025 | | 2025 |
| Planar-Staggered Array For DCNN Accelerators H Veluri, A Thean, Y Li, B Tang US Patent 20,240,028,880, 2025 | | 2025 |
| Planar-Staggered Array for DCNN Accelerators H Veluri, VYA Thean, Y Li, B Tang WO Patent WO/2022/124,993, 2022 | | 2022 |
