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WO2016069003A1 - Cellule d'alimentation électrique de secours dans un dispositif mémoire - Google Patents

Cellule d'alimentation électrique de secours dans un dispositif mémoire Download PDF

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Publication number
WO2016069003A1
WO2016069003A1 PCT/US2014/063490 US2014063490W WO2016069003A1 WO 2016069003 A1 WO2016069003 A1 WO 2016069003A1 US 2014063490 W US2014063490 W US 2014063490W WO 2016069003 A1 WO2016069003 A1 WO 2016069003A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
memory
power
volatile memory
memory device
Prior art date
Application number
PCT/US2014/063490
Other languages
English (en)
Inventor
Hai Ngoc Nguyen
Han Wang
Patrick A. Raymond
Raghavan V. Venugopal
Original Assignee
Hewlett Packard Enterprise Development Lp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Enterprise Development Lp filed Critical Hewlett Packard Enterprise Development Lp
Priority to PCT/US2014/063490 priority Critical patent/WO2016069003A1/fr
Priority to TW104133179A priority patent/TW201618094A/zh
Publication of WO2016069003A1 publication Critical patent/WO2016069003A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/141—Battery and back-up supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
    • H02J9/061—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for DC powered loads
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC

Definitions

  • Servers may provide architectures for backing up data to flash or persistent memory as well as back-up power sources for powering this back-up of data after the loss of power.
  • Backup power supplies may sometimes include energy components such as capacitors or batteries.
  • Figure 1 illustrates a block diagram of an example of a memory device including a back-up power supply cell according to the present disclosure
  • Figure 2 illustrates a block diagram of an example of a memory device including a back-up power supply cell according to the present disclosure
  • Figure 3 illustrates a flow diagram of an example method for a backup power supply according to the present disclosure.
  • a back-up power supply system can include a memory device.
  • the memory device can store data used by a computing device.
  • a backup power supply system can include an integrated back-up power supply cell.
  • the back-up power supply cell can provide back-up power to memory integrated in the memory device.
  • the back-up power can be provided to the memory if a primary power supply fails.
  • a removal of a primary power supply can be scheduled or un-scheduled.
  • a scheduled removal of the primary power supply can be the result of scheduled maintenance on the computing device and/or the memory device.
  • a scheduled removal of the primary power supply can be an intentional power down of the number of nodes and/or the number of loads to add and/or remove nodes to a chassis and/or network connected to a primary power supply.
  • a scheduled removal of the primary power supply can be an intentional power down to add and/or remove one or more loads to or from one or more nodes.
  • An un-scheduled primary power supply removal can be a failure in the primary power supply.
  • An un-scheduled primary power supply removal can occur when, for example, the primary power supply fails momentarily and/or for an extended period of time.
  • a backup power supply can be a secondary power supply.
  • a back-up power supply can provide back-up power to the computing device and/or the memory device via a back-up power supply cell.
  • back-up services are provided to a memory device via a back-up power supply cell that is not integrated in the memory device.
  • Providing back-up services via un-integrated cell requires infrastructure to provide the power from the un-integrated cells to the memory device.
  • the un-integrated cell and the associated infrastructure can increase cost associated with providing services associated with the memory device.
  • a memory device is defined as a device that provides memory services to a computing device.
  • a memory device can be Dual In-Line Memory Modules (DIMMs) and/or Non-Volatile Dual In-Line Memory Modules (NVDIMMs), among other types of memory modules.
  • DIMMs Dual In-Line Memory Modules
  • NVDIMMs Non-Volatile Dual In-Line Memory Modules
  • a memory device can include memory (e.g., a memory chip).
  • memory can include non-volatile memory (e.g., persistent memory) and/or volatile memory (e.g., non-persistent memory).
  • memory can include cache memory, Random Access Memory (RAM) and/or Non-Volatile Random Access Memory (NVRAM), among other types of memory.
  • RAM Random Access Memory
  • NVRAM Non-Volatile Random Access Memory
  • the memory can be integrated in the memory device.
  • the memory device can include a circuit board.
  • the memory can be coupled to the circuit board.
  • the memory can be a memory chip that is coupled to the circuit board via a number of electrical connections using conductive tracks, pads, and other features etched into the circuit board.
  • a back-up power supply cell can provide back-up power to the memory.
  • the back-up power supply cell can also be integrated in memory device. That is, the back-up power supply cell can be coupled to the circuity board via a number of electrical connections using conductive tracks, pads, and other features etched into the circuit board of the memory device.
  • Providing an integrated back-up power supply cell can reduce the cost of providing back-up services as compared to the use of un-integrated cells.
  • Providing back-up power services via integrated back-up power supply cells does not require infrastructure associated with un-integrated cells and the costs of providing the infrastructure.
  • Figure 1 illustrates a block diagram of an example of a memory device including a back-up power supply cell according to the present disclosure.
  • the memory device 100 includes memory in the form of memory chips 1 18-1 , 1 18-2, 1 18-3, 1 18- 4, 1 18-5, 1 18-6, 1 18-7, 1 18-8, 1 18-9, 1 18-10, 1 18-1 1 , 1 18-12, 1 18-13, 1 18-14, 1 18-15, 1 18-16, and 1 18-17 (e.g., referred to generally as memory 1 18), and a back-up power supply cell 108.
  • the memory device 100 also includes a power regulator 104, a controller 106, a charger 1 10, a discharging control circuitry 1 12, a power switch 1 14, and/or a plurality of pins 102.
  • memory device 100 may be a non- transitory storage medium, where the term "non-transitory" does not encompass transitory propagating signals.
  • the back-up power supply cell 108 is a device that provides back-up power.
  • a cell can be a battery, among other backup power devices.
  • the back-up power supply cell 108 can be controlled via controller 106.
  • Controller 106 can determine a charge level associated with the back-up power supply cell 108.
  • the controller 106 can activate a charger 1 10 to charge the back-up power supply cell 108.
  • the controller 106 can deactivate the charger 1 10 to stop the back-up power supply cell 108 from being charged.
  • the charger 1 10 can be used to charge the back-up power supply cell 108 when the back-up power supply cell 108 charge level is below a threshold value.
  • the charger 1 10 can be controlled by the controller 106 to charge the backup power supply cell 108 if the charge level is below a 95% charge.
  • a charger 1 10 can charge the back-up power supply cell 108 at an initiation (e.g., start-up) of an associated computing device and/or after primary power has been restored following primary power failure, for example.
  • the charger 1 10 can receive power from the power regulator 104.
  • the power regulator 104 can receive power from the pins 102.
  • the pins 102 can receive power from the computing device.
  • the power provided through the pins 102 can be associated with a higher voltage than the power needed to charge bell 108.
  • the power provided through the pins 102 can be 12 volts (v).
  • the power regulator 104 can regulate the 12v to a voltage suitable to charge the cell 108.
  • the power regulator 104 can regulate the 12v input power to an 8v power output that can be used by the charger 1 10 to charge the cell 108.
  • the power regulator 104 can regulate the 12v to a voltage that is higher or lower than 8v.
  • the controller 106 can provide back-up power to memory 1 18 in the case of primary power failure.
  • the controller 106 can activate the discharging control circuitry 1 12 to discharge the back-up power supply cell 108.
  • the controller can activate discharge control circuitry 1 12 to drain the back-up power supply cell 108.
  • the back-up power can be channeled through discharging control circuitry 1 12 and the power switch 1 14 to the memory 1 18.
  • the controller can activate the power switch 1 14 to provide the back-up power to the memory 1 18 in the case of primary power failure. However, if there is no primary power failure, the power switch can be activated to drain the backup power through the pins 102.
  • the pins 102 are a coupling point between the memory device 100 and a computing device.
  • the pins 102 can be used to transfer data from the memory 1 18 to the computing device and to transfer power to and from the backup power supply cell 108.
  • the pins 102 can confirm to a given layout used by the memory device 100.
  • the bus 1 16 can be used to transfer data to and from the memory 1 18.
  • the bus can be a memory input output (I/O) bus.
  • the memory 1 18 in Figure 1 is volatile memory.
  • each of the memory chips associated with memory 1 18 can be a RAM.
  • the memory 1 18 can retain data stored in the memory chips as long as the memory 1 18 receives power. In the occurrence of a primary power outage, the volatile memory chip loose the data stored in the memory.
  • the controller 106 and/or a processor associated with the computing device can detect a failure in the primary power supply.
  • the controller 106 can place the memory chips in one of a number of power modes.
  • Power modes associated with the memory 1 18 can define how the device consumes primary power and/or back-up power.
  • the controller 106 can place the memory 1 18 in a self-refresh mode and/or in a back-up power mode.
  • a back-up power mode is further defined in Figure 2.
  • a self-refresh mode provides the ability to suspend operation of the controller 106 to save power without losing data stored in the memory 1 18.
  • the data cannot be retrieved from memory 1 18 and data cannot be saved into memory 1 18.
  • Placing memory 1 18 in a self-refresh mode also saves power by reducing the refresh rate associated with memory 1 18.
  • placing memory 1 18 in self-refresh mode can save a greater amount of power than placing memory 1 18 in a back-up power mode or a mode associated with normal operation of the memory 1 18.
  • the memory 1 18 draws power from the cell 108.
  • the power drawn from the cells 108 is only sufficient to retain data stored in memory 1 18.
  • the memory 1 18 draws power indefinitely until primary power is returned to memory device 100.
  • the controller 106 can be activated and the memory 1 18 can be placed in a mode associated with normal operation on the memory 1 18.
  • the controller 106 can deactivate the back-up power supply cell 108 by deactivating the discharging control circuitry 1 12.
  • the controller can also charge the back-up power supply cell by activating the charger 1 10.
  • the volatile memory 1 18 can retain the data stored in memory 1 18 during primary power failure without the use of a back-up power supply that is not integrated in the memory device 100. That is, the memory device 100 can be persistent memory without the use of non-volatile memory.
  • FIG. 2 illustrates a block diagram of an example of a memory device including a back-up power supply cell according to the present disclosure.
  • the memory device 200 includes memory in the form of volatile memory chips 218-1 , 218-2, 218-3, 218-4, 218-5, 218-6, 218-7, 218-8, 218-9 (e.g., referred to herein as volatile memory 218) which are analogous to memory chips 1 18-1 to 18-17 in Figure 1 , and non-volatile memory chips 232-1 , 232-2, 232-3, 232-4, 232-5, 232-6, 232-7, 232-8 (e.g., referred to herein as non-volatile memory 232).
  • volatile memory chips 218-1 , 218-2, 218-3, 218-4, 218-5, 218-6, 218-7, 218-8, 218-9 e.g., referred to herein as volatile memory 2128
  • the memory device 200 also includes a back-up power supply cell 208 which is analogous to back-up power supply cell 108. In a number of examples, more or less volatile memory chips 218-1 to 218-9 and nonvolatile memory chips 232-1 to 232-8 than those shown herein can be included in the memory device 200.
  • the memory device 200 also includes a power regulator 204, a controller 206, a charger 210, a discharging control circuitry 212, a power switch 214, and a plurality of pins 202 that are analogous to a power regulator 104, a controller 106, a charger 1 10, a discharging control circuitry 1 12, a power switch 1 14, and a plurality of pins 102.
  • Figure 2 provides an example of providing back-up power to transfer data stored in the volatile memory 218 to non-volatile memory 232.
  • the controller 206 can identify a primary power failure and place the volatile memory 218 in a self-refresh mode.
  • the controller 206 can sequentially change the power mode associated with the number of volatile memory 218 to allow data stored in the volatile memory 218 to be transferred to non-volatile memory 232.
  • Changing the power mode associated with the volatile memory 218-1 to allow transfer of data can include changing from self-refresh mode to a mode that consumes more energy.
  • a power mode associated with the volatile memory 218 can be changed from a self- refresh mode to a back-up power mode.
  • the back-up power mode can allow a transfer of data from the volatile memory 218.
  • the back-up power mode can consume more energy than the self-refresh mode because the back-up power mode receives instructions from an activated controller and because the backup power mode can support data transfers from volatile memory 218.
  • volatile memory 218 in a back-up power mode can use less energy than a normal operation of the volatile memory 218.
  • a power mode associated with the volatile memory 218 can be sequentially changed from a self-refresh mode to a back-up power mode. Sequentially changing volatile memory 218 from a self-refresh mode to a back-up power mode can include changing each of the volatile memory chips individually one after another. For example, the volatile memory chip 218-1 can be changed to a back-up power mode before the other volatile memory chips 218-2 to 218-9 are changed to a back-up power mode. The volatile memory chip 218-2 can be changed to a backup power mode after the volatile memory chip 218-1 is changed to the back-up power mode but before the other volatile memory chips 218-3 to 218-9 are changed to the back-up power mode.
  • the volatile memory chip 218-3 can be changed to the back-up power mode after the volatile memory chips 218-1 and 218-2 are changed to the back-up power mode but before the other volatile memory chips 218-4 to 218-9 are changed to the back-up power mode.
  • the volatile memory chip 218-4 can be changed to the back-up power mode after the volatile memory chips 218- 1 and 218-3 are changed to the back-up power mode but before the other volatile memory chips 218-5 to 218-9 are changed to the back-up power mode.
  • the volatile memory chip 218-5 can be changed to the back-up power mode after the volatile memory chips 218-1 and 218-4 are changed to the back-up power mode but before the other volatile memory chips 218-6 to 218-9 are changed to the back-up power mode.
  • the volatile memory chip 218-7 can be changed to the back-up power mode after the volatile memory chips 218-1 and 218-6 are changed to the back-up power mode but before the other volatile memory chips 218- 8 to 218-9 are changed to the back-up power mode.
  • the volatile memory chip 218-8 can be changed to the back-up power mode after the volatile memory chips 218-1 and 218-7 are changed to the back-up power mode but before the volatile memory chip 218-9 is changed to the back-up power mode.
  • the volatile memory chip 218-9 can be changed to the back-up power mode after the volatile memory chips 218-1 and 218-8 are changed to the back-up power mode.
  • Transferring data from the volatile memory 218 to the non-volatile memory 232 can store that data such that the primary power failure does not affect the ability to recall the data (e.g., the data is not lost) from memory device 200 when the primary power is activated.
  • the data can be transferred from volatile memory 218 to non-volatile memory 232 via bus 230.
  • bus 230 can be analogous to bus 1 16 and/or it can be a different bus.
  • bus 230 can be used to only transfer data between volatile memory 218 and non-volatile memory 232 and not to transfer data to the computing device coupled to the memory device 200.
  • the transfer of data can be performed round robin.
  • Transferring data round robin can include completing the transfer of data from a first memory chip before initiating a transfer of data from a second memory chip.
  • the transfer of data stored in the volatile memory chip 218-1 can be initiated and completed before the data stored in volatile memory chips 218-2 to 218-9 is transferred.
  • the transfer of data stored in the volatile memory chip 218-2 can be initiated and completed before the data stored in volatile memory chips 218-3 to 218-9 is transferred.
  • the transfer of data stored in the volatile memory chip 218-3 can be initiated and completed before the data stored in volatile memory chips 218-4 to 218-9 is transferred.
  • the transfer of data stored in the volatile memory chip 218-4 can be initiated and completed before the data stored in volatile memory chips 218-5 to 218-9 is transferred.
  • the transfer of data stored in the volatile memory chip 218- 5 can be initiated and completed before the data stored in volatile memory chips 218-6 to 218-9 is transferred.
  • the transfer of data stored in the volatile memory chip 218-6 can be initiated and completed before the data stored in volatile memory chips 218-7 to 218-9 is transferred.
  • the transfer of data stored in the volatile memory chip 218-7 can be initiated and completed before the data stored in volatile memory chips 218-8 to 218-9 is transferred.
  • the transfer of data stored in the volatile memory chip 218-8 can be initiated and completed before the data stored in volatile memory chip 218-9 is transferred.
  • the transferred of data stored in the volatile memory chip 218-9 can be initiated after the data stored in the volatile memory chips 218-1 to 218-8 has been transferred.
  • Transferring data round robin can maintain one volatile memory chip in back-up power mode and the remaining volatile memory chips in self-refresh mode. Maintaining only one volatile memory chip in back-up power mode while the remaining volatile memory chips are in self-refresh mode can save energy over maintaining all of the volatile memory chips 218 in back-up mode because volatile memory chips 218 in self-refresh mode consume less energy than volatile memory chips 218 in back-up mode.
  • Transferring data to non-volatile memory 232 can include activating all of the non-volatile memory chips at once or activating each of the non-volatile memory chips at a given time. For example, each of the non-volatile memory chips 232 can be activated round robin to receive and store the data from the volatile memory chips 218.
  • Activating one non-volatile memory chip at a time can save energy over activating all of the memory chips at once. Activating one non-volatile memory chip at a given time can occur when data transferred from the volatile memory 218 is only stored in one non-volatile memory chip at a given time.
  • FIG. 3 illustrates a flow diagram of an example method for a backup power supply according to the present disclosure.
  • a primary power failure can be detected by a controller in a memory device.
  • the controller in the memory device can be alerted of the power failure by a processor associated with the computing device coupled to the memory device and/or by analyzing the power provided by a number of pins associated with the memory device. For example, the controller can detect a change in voltage being provided by the pins.
  • the a back-up power supply cell that is integrated in the memory device can be activated to provide back-up power to volatile memory integrated in the memory device.
  • the back-up power supply can be charged before being activated from power provided via the pins associated with the memory device, wherein the pins are integrated in the memory device.
  • the pins can be integrated in the memory device when they are formed into the circuit board associated with the memory device.
  • the backup power supply can be charged via a connection point that is part of the back-up power supply and that receives power directly from the computing device and not from the pins associated with the memory device.
  • the data stored in volatile memory can be transferred to non-volatile memory.
  • the volatile memory can be integrated in the memory device.
  • the data can be transferred using back-up power from the back-up power supply cell.
  • the back-up power supply cell can be deactivated when the transfer of data from volatile memory to non-volatile memory is complete. Deactivating the back-up power supply during primary power failure can result in the data stored in the volatile memory being lost. However, the data stored in the non-volatile memory will not be lost.
  • the volatile memory in the memory device can function as non-volatile memory. Using volatile memory and non-volatile memory in the same memory device can decrease the cost of the memory device as compared to only using nonvolatile memory in the memory devices as volatile memory cost less than non-volatile memory.
  • logic is an alternative or additional processing resource to perform a particular action and/or function, etc., described herein, which includes hardware, e.g., various forms of transistor logic, application specific integrated circuits (ASICs), etc., as opposed to computer executable instructions, e.g., firmware, etc., stored in memory and executable by a processor.
  • ASICs application specific integrated circuits
  • a number of something can refer to one or more such things.
  • a number of widgets can refer to one or more widgets.
  • a plurality of something can refer to more than one of such things.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Business, Economics & Management (AREA)
  • Emergency Management (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Des modes de réalisation donnés à titre d'exemple concernent une alimentation électrique de secours dans une cellule mémoire. Par exemple, un système d'alimentation électrique de secours parallèle peut comprendre un dispositif mémoire. Le dispositif mémoire peut comprendre une mémoire qui est intégrée dans le dispositif mémoire. Le dispositif mémoire peut comprendre également une cellule d'alimentation électrique de secours qui est intégrée dans le dispositif mémoire et fournit une alimentation électrique de secours à la mémoire.
PCT/US2014/063490 2014-10-31 2014-10-31 Cellule d'alimentation électrique de secours dans un dispositif mémoire WO2016069003A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2014/063490 WO2016069003A1 (fr) 2014-10-31 2014-10-31 Cellule d'alimentation électrique de secours dans un dispositif mémoire
TW104133179A TW201618094A (zh) 2014-10-31 2015-10-08 記憶裝置中之備用電源供應單元

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2014/063490 WO2016069003A1 (fr) 2014-10-31 2014-10-31 Cellule d'alimentation électrique de secours dans un dispositif mémoire

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WO2016069003A1 true WO2016069003A1 (fr) 2016-05-06

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060015683A1 (en) * 2004-06-21 2006-01-19 Dot Hill Systems Corporation Raid controller using capacitor energy source to flush volatile cache data to non-volatile memory during main power outage
US20060080515A1 (en) * 2004-10-12 2006-04-13 Lefthand Networks, Inc. Non-Volatile Memory Backup for Network Storage System
US20090249008A1 (en) * 2008-03-27 2009-10-01 Hitachi, Ltd. Disk array device
US20130142001A1 (en) * 2008-07-10 2013-06-06 Sanmina-Sci Corporation Battery-less cache memory module with integrated backup
WO2014040065A1 (fr) * 2012-09-10 2014-03-13 Texas Instruments Incorporated Informatique à base de réseau logique non volatil sur alimentation électrique incompatible

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060015683A1 (en) * 2004-06-21 2006-01-19 Dot Hill Systems Corporation Raid controller using capacitor energy source to flush volatile cache data to non-volatile memory during main power outage
US20060080515A1 (en) * 2004-10-12 2006-04-13 Lefthand Networks, Inc. Non-Volatile Memory Backup for Network Storage System
US20090249008A1 (en) * 2008-03-27 2009-10-01 Hitachi, Ltd. Disk array device
US20130142001A1 (en) * 2008-07-10 2013-06-06 Sanmina-Sci Corporation Battery-less cache memory module with integrated backup
WO2014040065A1 (fr) * 2012-09-10 2014-03-13 Texas Instruments Incorporated Informatique à base de réseau logique non volatil sur alimentation électrique incompatible

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