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WO2002008911A1 - Data processing system - Google Patents

Data processing system Download PDF

Info

Publication number
WO2002008911A1
WO2002008911A1 PCT/JP2000/004906 JP0004906W WO0208911A1 WO 2002008911 A1 WO2002008911 A1 WO 2002008911A1 JP 0004906 W JP0004906 W JP 0004906W WO 0208911 A1 WO0208911 A1 WO 0208911A1
Authority
WO
WIPO (PCT)
Prior art keywords
information
page
way
cache memory
reusability
Prior art date
Application number
PCT/JP2000/004906
Other languages
French (fr)
Japanese (ja)
Inventor
Yasuhiko Saitou
Masahiro Kainaga
Original Assignee
Hitachi,Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi,Ltd filed Critical Hitachi,Ltd
Priority to PCT/JP2000/004906 priority Critical patent/WO2002008911A1/en
Publication of WO2002008911A1 publication Critical patent/WO2002008911A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A data processing system comprises a page information table (15) for holding page information on a page constituting an address space of a program to be executed and a cache memory (5) of multi-way type. A way specifying field (42) for specifying a way of the cache memory is provided in each page information field (40) in the page information table. The cache memory selects a cache fill object way from the ways specified by the way specifying fields corresponding to the page of the access address in replacing stored information in response to a cache miss. Thus, a way specifying field can be so set that the way of storage destination of the page containing information of high spatial reusability may be different from that of the page containing information of low reusability. As a result, in replacing stored information in response to a cache miss, a failure that information of relatively high reusability is expelled from the cache memory by information of relatively low reusability.
PCT/JP2000/004906 2000-07-24 2000-07-24 Data processing system WO2002008911A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2000/004906 WO2002008911A1 (en) 2000-07-24 2000-07-24 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2000/004906 WO2002008911A1 (en) 2000-07-24 2000-07-24 Data processing system

Publications (1)

Publication Number Publication Date
WO2002008911A1 true WO2002008911A1 (en) 2002-01-31

Family

ID=11736280

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/004906 WO2002008911A1 (en) 2000-07-24 2000-07-24 Data processing system

Country Status (1)

Country Link
WO (1) WO2002008911A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005122506A (en) * 2003-10-17 2005-05-12 Matsushita Electric Ind Co Ltd Compiler device
WO2005048112A1 (en) * 2003-11-12 2005-05-26 Matsushita Electric Industrial Co., Ltd. Cache memory and control method thereof
JP2009098933A (en) * 2007-10-17 2009-05-07 Nec Corp Method of fixing registration destination way, processor and information processing device
JP2011081836A (en) * 2010-12-20 2011-04-21 Panasonic Corp Compiler device
WO2013098919A1 (en) * 2011-12-26 2013-07-04 ルネサスエレクトロニクス株式会社 Data processing device
JPWO2013098919A1 (en) * 2011-12-26 2015-04-30 ルネサスエレクトロニクス株式会社 Data processing device
JP2016122474A (en) * 2016-04-05 2016-07-07 ルネサスエレクトロニクス株式会社 Data processing device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194564A (en) * 1986-02-21 1987-08-27 Nec Corp Cache memory substituting system
JPH0449446A (en) * 1990-06-19 1992-02-18 Nec Corp System for controlling plural caches
JPH08212135A (en) * 1995-02-06 1996-08-20 Hitachi Ltd Information processing device
EP0856797A1 (en) * 1997-01-30 1998-08-05 STMicroelectronics Limited A cache system for concurrent processes

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194564A (en) * 1986-02-21 1987-08-27 Nec Corp Cache memory substituting system
JPH0449446A (en) * 1990-06-19 1992-02-18 Nec Corp System for controlling plural caches
JPH08212135A (en) * 1995-02-06 1996-08-20 Hitachi Ltd Information processing device
EP0856797A1 (en) * 1997-01-30 1998-08-05 STMicroelectronics Limited A cache system for concurrent processes

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NEC Gihou, Vol.48, No. 8, 11 September, 1995, Hiroki MACHIDA et al., "V850 Family muke Kouseinou C Complier CA850", pages 42 to 47, *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005122506A (en) * 2003-10-17 2005-05-12 Matsushita Electric Ind Co Ltd Compiler device
WO2005048112A1 (en) * 2003-11-12 2005-05-26 Matsushita Electric Industrial Co., Ltd. Cache memory and control method thereof
US7502887B2 (en) 2003-11-12 2009-03-10 Panasonic Corporation N-way set associative cache memory and control method thereof
JP2009098933A (en) * 2007-10-17 2009-05-07 Nec Corp Method of fixing registration destination way, processor and information processing device
JP2011081836A (en) * 2010-12-20 2011-04-21 Panasonic Corp Compiler device
WO2013098919A1 (en) * 2011-12-26 2013-07-04 ルネサスエレクトロニクス株式会社 Data processing device
JPWO2013098919A1 (en) * 2011-12-26 2015-04-30 ルネサスエレクトロニクス株式会社 Data processing device
US9495299B2 (en) 2011-12-26 2016-11-15 Renesas Electronics Corporation Data processing device utilizing way selection of set associative cache memory based on select data such as parity data
JP2016122474A (en) * 2016-04-05 2016-07-07 ルネサスエレクトロニクス株式会社 Data processing device

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