WO2001067271A1

WO2001067271A1 - Information processing device

Info

Publication number: WO2001067271A1
Application number: PCT/JP2000/001475
Authority: WO
Inventors: Hiroshi Hatae; Hiromi Watanabe
Original assignee: Hitachi, Ltd.
Priority date: 2000-03-10
Filing date: 2000-03-10
Publication date: 2001-09-13

Abstract

Means is provided for improving the performance or processing speed of an information processor that comprises a host CPU as a master and an accelerator as a slave connected with the master. The host CPU has a Neumann architecture, and the CPU in the accelerator has a Harvard architecture. More specifically, a storage shared by both CPUs includes a selector, which connects the storage selectively with the buses associated with the individual CPUs. The shared memory is composed of dual-port memory. The configuration increases the processing speed of the information processor comprising a master CPU and a slave CPU.

Description

Description Information processing equipment Technical field

The present invention relates to an information processing apparatus, and in particular, relates to two CPUs (central processing units) having a master-slave relationship, specifically, a host CPU and a CPU in an accelerator. The present invention relates to an information processing device having two CPUs. Background art

At present, portable terminal devices are becoming popular. In general, this mobile terminal is often composed of a host CPU as a master, and an accelerator as a slave that assists the processing of the host CPU. For example, when decoding MPEG-4, the audio part is processed by the host CPU, and the image part is left to a dedicated LSI (axelator) that processes MPEG4. In addition, this portable terminal is required to be able to perform signal processing of a plurality of standards with low power consumption. For this reason, the LSI used inside the device is used from a combination of the conventional host CPU and an accelerator configured with hardware to a combination of the host CPU and an accelerator that has a built-in processor and operates with software. It is possible. Hereinafter, the processor incorporated in the accelerator is referred to as an accelerator CPU. In such a configuration, the processing content can be changed by changing the program transferred to the accelerator. In other words, by changing the program to be transferred, signal processing of multiple standards can be performed. An example of this case is shown in FIG. In this configuration, the first CPU (CPU 1), which acts as the host CPU, The address bus (AB) and data bus (DB) connected to the first CPU and accelerator, the accelerator CPU (AC PU) provided in the accelerator (AC), and the accelerator CPU Internal address bus (INTAB) and internal data bus (INTDB), a first selector (SEL1) and a second selector for selectively connecting each bus to memory (RAM) (SEL 2). As an operation, before starting, the first selector and the second selector are switched to the bus side of the first CPU, and the program of the accelerator CPU is transferred to the memory. When the accelerator is activated, the selector is switched to the bus of the accelerator CPU (AC PU), the program stored in the memory is read, and the accelerator CPU executes the processing.

By the way, the CPU in the accelerator connected to the CPU as the master is often composed of about five pipelines. The contents of the five stages are instruction fetch, instruction decode, execution, memory access, and write-back. In the instruction fetch and memory access stages, contention occurs because both use the address bus and data bus of the accelerator CPU. For this reason, there is a problem that the performance of the information processing device, that is, the processing speed is reduced, because measures are usually taken to delay one of the stages by one clock.

The related related patent application publications include Japanese Patent Application Laid-Open Nos. Hei 5-94305, Hei 5-233 191, Hei 6-19704 and Hei 10-254 776. There are seven. However, none of the publications discloses or suggests the problems in the above-described configuration, and it can be said that there is no publication showing the configuration of the present invention shown in this specification.

Therefore, an object of the present invention is to provide an information processing apparatus having a CPU serving as a master and a CPU serving as a slave. An object of the present invention is to provide an information processing apparatus which prevents contention for access and does not degrade performance.

A further object of the invention is of the Neumann type. An object of the present invention is to provide a high-performance information processing device by using a PU and a harbor type CPU.

Other objects of the present invention will become apparent from the present specification and the drawings. Disclosure of the invention

In order to achieve the above object, according to the first aspect of the present invention, in an information processing apparatus having a first central processing unit, a second central processing unit, and a storage device, the first central processing unit includes an instruction. And the data are output to the storage device via the same bus, and the second central processing unit accesses the storage device via the instruction bus and the data bus.

According to the invention of claim 7, the first central processing unit, a first bus connected to the first central processing unit to transfer instructions and data, a second central processing unit, A second bus connected to the central processing unit for transferring instructions; a third bus connected to the second central processing unit for transferring data; a storage device; a first bus and a second bus A first selection circuit connected to the first bus or the second bus and connected to the storage device by selecting the first bus or the second bus; and a first bus or the third bus connected to the first bus and the third bus. A second selection circuit for selecting a bus and connecting it to the storage device.

The invention according to claim 10 is characterized in that the first central processing unit, a first bus connected to the first central processing unit to transfer instructions and data, a second central processing unit, A second bus connected to the second central processing unit; a third bus connected to the second central processing unit; a first memory port and a second memory. A storage device having a report, and a first selection circuit connected to the first bus and the second bus, for selecting the first bus or the second bus and connecting to the first memory port of the storage device And the third bus is connected to a second memory port of the storage device.

According to the invention of claim 14, there is provided a first central processing unit having a Neumann architecture, and a second central processing unit having a Harvard architecture for processing a program transferred by the first central processing unit. It is like that.

According to the invention of claim 15, in the information processing apparatus of claim 14, the first central processing unit is connected to the storage device via the first bus, and the second central processing unit is connected to the second central processing unit. It is connected to a storage device via a bus and a third bus.

According to a sixteenth aspect of the present invention, in the information processing device according to the fourteenth or fifteenth aspect, the storage device is a dual port memory having a first memory port and a second memory port.

According to the invention of claim 19, in the information processing apparatus of claim 14 or 15, the storage device has a first storage device for storing instructions and a second storage device for storing data. The information processing apparatus further includes: a first selection circuit that selectively connects the first bus and the second bus to the first storage device; and a first bus and a third bus. And a second selection circuit connected to the second storage device.

As described above, by using the present invention, the accelerator connected to the host CPU can use the processor of the herb-and-door architecture, so that the processing content can be made programmable. Further, since instruction fetch and memory access can be operated in parallel, a high-speed information processing device can be realized. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a configuration diagram of the information processing apparatus according to the first embodiment. FIG. 2 is a detailed configuration diagram of the control block shown in FIG. FIG. 3 is a detailed configuration diagram of the logic block shown in FIG. FIG. 4 is a configuration diagram of the information processing apparatus according to the second embodiment. FIG. 5 is a diagram showing a first allocation of instruction and data areas. FIG. 6 is a diagram showing a second allocation of instruction and data areas. FIG. 7 is a configuration diagram of the information processing device according to the third embodiment. FIG. 8 is a configuration diagram of the information processing apparatus according to the fourth embodiment. FIG. 9 is a configuration diagram according to the information processing apparatus of the fifth embodiment. FIG. 10 is a configuration diagram of a conventional information processing apparatus. BEST MODE FOR CARRYING OUT THE INVENTION

The first embodiment will be described with reference to FIG. The information processing device shown in the present embodiment is used in a portable information terminal, although not particularly limited. It consists of a host CPU acting as a master and an accelerator acting as a slave connected to it. For example, the host CPU may perform voice processing, and the accelerator may process MPEG4. However, there is no particular limitation. In FIG. 1, CPU 1 is a first CPU as a host CPU, and CPU 2 is a second CPU as a CPU in an accelerator (AC). Although not particularly limited, the CPU of this embodiment performs a five-stage pipeline process including instruction fetch, instruction decode, execution, memory access, and write-back. What has been described above is not limited to the first embodiment, but can be applied to the embodiments described later. CT L controls the second CPU, CPU 2, A control block for controlling a first selector (SEL 1), a ^second selector (SEL 2), a third selector (SEL 3), and a fourth selector (SEL 4) described later. It is. The control block (CTL) is connected to the second CPU, CPU 2 and the first to fourth selectors (SEL1, SEL2, SEL3, SEL4) by signal lines. The control signal for starting the second CPU (CPU 2) and the control signal to each selector (SEL1, SEL2, SEL3, SEL4) are transmitted via the signal line. The first CPU (CPU 1) is connected to the address bus (AB) and the data bus (DB). The second CPU (CPU 2) is connected to the instruction address bus (IAB), the instruction data bus (IDB), the data address bus (DAB), and the data bus for data (DDB). The first selector (SEL 1) has an address bus (AB) connected to the first CPU (CPU 1) and an instruction address bus (I PU) connected to the second CPU (CPU 2). AB). The second selector (SEL 2) switches between the data bus (DB) connected to the first CPU (CPU 1) and the instruction data bus (IDB) connected to the second CPU. is there. The third selector (SEL3) has an address bus (AB) connected to the first CPU (CPU1) and a data address bus (DAB) connected to the second CPU (CPU2). ) This is a selector that switches between and. The fourth selector (SEL 4) has a data bus (DB) connected to the first CPU (CPU 1) and a data bus (DDB) connected to the second CPU (CPU 2). ). The first to fourth selectors are configured to connect any of the connected buses to the memory by the control signal, but there is a problem even if there is a state where none of the buses is connected to the memory. There is no. The instruction memory (IM) is a memory for storing instructions of the second CPU (CPU 2). An address terminal is connected to an address bus (AB) or an instruction address bus (IAB) via a first selector (SEL 1), and a data terminal is connected to a second selector (SEL 2). ) Is connected to a data bus (DB) or an instruction data bus (IDB). The data storage device (DM) is a storage device for instructions for storing data. The address terminal is connected to an address bus (AB) or a data address bus (DAB) via a third selector (SEL3). The data terminal is connected to a data bus (DB) or a data bus for data (DDB) via a fourth selector (SEL 4). The instruction storage device (IM) and the data storage device of this embodiment are RAM (random access memory), but they are not part of the essence of the present invention. There is no particular problem even with a non-volatile memory. The data address bus (DAB) and data data bus (DDB) connected to the second CPU are connected to the logic block (BLK) built in the accelerator (AC). The configuration of this embodiment is characterized in that the second CPU has a Harvard architecture in which an instruction bus (IAB, IDB) and a data bus (DAB, DDB) are separated. The first CPU has a so-called Neumann architecture in which an instruction bus and a data bus are not separated. That is, in the above description, the instruction address, the data address, and the data are transferred to the address bus (AB), and the instruction data and the data data are transferred to the data bus (DB). In this specification, the terms Harvard architecture, Harvard type, and Neumann architecture or Neumann type are used, but other names may be used without departing from the spirit of this specification. No problem. In addition, the first CPU and the second CPU shown in the first embodiment take the memory efficiency into consideration when storing instructions into memory. 475

Although it is possible to adopt a configuration in which 8-bit instructions are processed, a configuration in which 32-bit instructions are processed in order to have more instructions may be used. . Further, a configuration may be employed in which instructions having a mixed length of 16 bits and 32 bits are processed, and the first and second CPUs may be configured to process instructions having different instruction lengths. However, it is not particularly limited in all the embodiments. Also, in the above description, it seems that instructions, data, and addresses are mixed at first glance, but there are data based on the relationship between address and data and data based on the relationship between instruction and data. Because it is. However, it is easily understood by those skilled in the art that the instruction data, the data data, and the mere data have meanings.

In FIG. 2, the control block (CTL) shown in FIG. 1 will be described in detail. The control block has therein a control circuit (CTLC) connected to an address bus (AB) connected to the first CPU and a data bus (DB). The control circuit (CT LC) decodes the address supplied from the address bus (AB), and if the supplied address indicates the address of the control register (CTLR), the control register (CTLR) CT LR) is written. According to the value of the 0th bit (O bit) of the control register (CT LR), the control signal for activating the second CPU (CPU 2) is transmitted via the signal line to the second CPU. Supplied to In addition, a control signal is supplied to the first to fourth selectors via signal lines according to the value of the first bit (Ibit) of the control register (CTLR).

FIG. 3 describes the logical block (BLK) shown in FIG. 1 in detail. The logical block (BLK) is a block configured with a hardware card, although not particularly limited. In this embodiment, as an example, DC The block that performs T (discretecosinetransform) processing is described. The logic block (BLK) has a control circuit (BLKC) connected to a data address bus (DAB) connected to the second CPU and a data bus for data (DDB). The control circuit (BLKC) in the logic block decodes the address supplied via the data address bus (DAB), and buffers (BLKB) and registers (BLKR) according to the supplied address. Are controlled. The data to be processed is written from the data bus for data (DDB) to the buffer (B LKB), and then "1" is written to the start bit of the register (B LKR). (DCTU) starts operation and writes the conversion result back to the buffer (B LKB).

Next, the operation of the present embodiment described above will be described. First, in the power-on reset state, all bits of the control register (CT LR) in the control block (CTL) shown in Fig. 2 are 0. Therefore, the signal line for activating the second CPU is also in the “L” state, and the second CPU (CPU 2) is stopped. Also, the signal lines for controlling the first to fourth selectors (SEL1, SEL2, SEL3, SEL4) are also in the "L" state. If the signal line for controlling the selector is in the “L” state, the first selector (SEL 1) and the third selector (SEL 3) are connected to the address bus connected to the first CPU. (AB) is selected, and the instruction storage device (IM) and data storage device (DM) are connected to the address bus (AB). Similarly, if the signal line for controlling the selector is in the “L” state, the second selector (SEL 2) and the fourth selector (SEL 4) are connected to the data connected to the first CPU. Select the bus (DB) and the instruction storage (IM) and data storage (DM) are the data bus (DB) Connected. That is, when the signal line for controlling the first to fourth selectors is "L", the instruction storage device and the data storage device are connected to the first CPU. In this state, when operating the second CPU, the first CPU (CPU 1) is connected to the address bus (AB), the first selector (SEL 1), and the data bus (DB). through the ^second selector (SEL 2), the instruction for the second C PU (C PU 2) was transferred to the instruction Symbol憶device (IM), further, the address bus (AB) a third selector The data for the second CPU (CPU2) is transferred to the data storage device (DM) via the data bus (DB) and the fourth selector (SEL4). Further, the control circuit (CT LC) in the control block (CTL) writes "1" to the first bit (1 bit) of the control register (CT LR). As a result, the control signals for controlling the respective selectors become “H”, and the first selector (SEL 1) sets the instruction address bus (I 2) connected to the second CPU (CPU 2). AB) is connected to the address terminal of the instruction storage device (IM), and the second selector (SEL 2) is connected to the instruction data bus connected to the second CPU (CPU 2).

(I DB) and the data terminal of the instruction storage device (IM). The third selector (SEL3) connects the data address bus (DAB) connected to the second CPU (CPU2) to the address terminal of the data storage device (DM), and the fourth selector (SEL3). Selector (SEL 4) connects the data bus (DDB) connected to the second CPU (CPU 2) to the data terminal of the data storage device (DM). Next, write "1" to the 0th bit (O bit) of the control register (CT LR) in the control block (CTL). As a result, the control signal transmitted through the signal line connected to the second CPU (CPU 2) becomes “H”, and the second CPU is activated. By the above operation, the second CPU (CPU 2) The processing is started using the instructions stored in the storage device (IM) and the data stored in the data storage device (DM).

With the configuration of the information processing apparatus of the first embodiment described above, the central processing unit in the accelerator (AC) connected to the first CPU performing host-like operation (the second processing in the present embodiment) It is possible to use a Harvard architecture CPU in which the instruction bus and the data bus are separated for the CPU. Therefore, when the second CPU in the accelerator performs memory access, it is possible to access data and instructions on different buses, which may occur during pipeline processing. High contention between buses does not occur, and there is no need to delay the pipeline stage for processing, thereby enabling higher performance operation without lowering the processing speed.

Example 2>

Next, a second embodiment will be described with reference to FIG. This embodiment is characterized in that a dual port memory (DPM) is used instead of the instruction storage device (IM) and the data storage device (DM) in the first embodiment. However, the dual-port memory is sometimes called a two-port memory.

The configuration of the second embodiment will be described focusing on differences from the first embodiment. Also in the second embodiment, although not particularly limited, the first CPU (CPU 1) is a host CPU, and the second CPU (CPU 2) is a CPU provided in an accelerator (AC). The control block (CTL) controls the CPU 2 which is the second PU, and controls the first selector (SEL 1) and the second selector (SEL 2) described later. Do. The control block (CTL) is connected to the second CPU, CPU 2 and the first selector (SEL 1) and the second selector (SEL 2) by signal lines, and via those signal lines. To start the second CPU (CPU 2) Control signal and the control signal to the first and second selectors (SEL1, SEL2). The first CPU (CPU 1) is connected to the address bus (AB) and the data bus (DB). The second CPU (CPU 2) is connected to the instruction address bus (IAB), the instruction data bus (IDB), the data address bus (DAB), and the data bus for data (DDB). The first selector (SEL 1) includes an address bus (AB) connected to the first CPU (CPU 1) and an instruction address bus (AB) connected to the second CPU (CPU 2). I AB). The second selector (SEL2) disconnects the data bus (DB) connected to the first CPU (CPU1) from the instruction data bus (IDB) connected to the second CPU. This is a selector for switching. The dual port memory (DPM) has a first memory port (P 1) and a second memory port (P 1), each of which comprises an address terminal for inputting an address and a data terminal for inputting and outputting data. P 2) is a memory that has two independent memory locations, and since it is conventionally known, its internal description is omitted. The dual-port memory (DPM) is a storage device for instructions of the second CPU (CPU 2) and instructions for storing data processed by the second CPU. The address terminal of the first port (P1) of the dual port memory (DPM) is connected to the address bus (AB) or the instruction address bus (IAB) via the first selector (SEL1) The data terminal is connected to a data bus (DB) or an instruction data bus (I DB) via a second selector (SEL 2). The address terminal of the second port (P2) of the dual-port memory is connected to the data address bus (DAB), and the data terminal is connected to the data bus for data (DDB). The internal configuration of the control block (CTL) and logical block (BLK) is not particularly limited, but is the same as the configuration shown in FIGS. 2 and 3. Further, the configuration of the second embodiment 75

13, the second CPU is a Harvard architecture in which the instruction bus (IAB, IDB) and the data bus (DAB, DDB) are separated. The first CPU has a so-called Neumann architecture in which the instruction bus and the data bus are not separated. That is, in the above description, the instruction address, the data address, and the power are transferred to the address bus (AB); and the instruction data and the data data are transferred to the data bus (DB).

An operation of the information processing apparatus according to the second embodiment will be described. First, in the power-on reset state, as in the first embodiment, the first selector (SEL1) connects the address bus (AB) connected to the first CPU (CPU1) to the dual-port memory (D PM) is connected to the address terminal of the first port (P 1), and the second selector (SEL 2) connects the data bus (DB) connected to the first CPU to the dual port memory. Connected to the data terminal of the first port (P 1). In this state, the first CPU (CPU 1) dual-ports the instruction and data for the second CPU (CPU 2) in the accelerator (AC) or a program in which the instruction and data are mixed. Via the first port of the remote memory. Next, as in the first embodiment, "1" is written to the first bit (1 bit) of the control register (CTLR) in the control block (CTL). As a result, the control signals for controlling the respective selectors become “H”, and the first selector connects the address terminal of the first port (P 1) of the dual port memory (DPM) to the second terminal. The instruction selector is connected to the instruction address bus (IAB) connected to the CPU (CPU 2), and the second selector is connected to the data port of the first port and the instruction data bus connected to the second CPU. (I DB). Furthermore, by writing "1" to bit 0 (O bit) of the control register in the control block, the second CPU (CPU 2) is activated. The second CPU is connected to the first port (P1) of the dual port memory (DPM), the instruction address bus (IAB), and the instruction data bus (IDB). Starts the fetch operation of the instruction executed by the second CPU stored in the CPU. At this time, the dual-port memory can access the same physical memory space in parallel from the two ports (Pl, P2), so the instruction buses (I AB, I DB ) And data buses (DAB, DDB) can operate in parallel.

In the second embodiment, the second CPU (CPU 2) in the accelerator (AC) has an instruction area and a data area to be accessed in the same physical space, so that the second CPU has a Harvard architecture. Even if you have one, it is possible to use a program in which instructions and data are mixed. Furthermore, the transfer of the program from the first CPU (CPU 1), which is the host CPU, can be performed at one time. Further, two selectors, which were required in the first embodiment, are now required. As described above, in the second embodiment, the hardware scale can be reduced as compared with the first embodiment, and the performance can be further improved. Also, because the same physical space can be used for instructions and data, the entire RAM space is 40% for the instruction area (IR) and 60% for the data area (DR) as shown in Figure 5. It can be used by dividing it into 60% in the instruction area (IR) and 40% in the data area (DR) as shown in Fig. 6. And the ratio of data can be flexibly changed and used. In the second embodiment, the selectors (SEL1, SEL2) are connected between the buses (AB, DB) connected to the first CPU and the instruction buses (IAB, IDB) of the second CPU. ), But the bus (AB, AB) connected to the first CPU and the data bus (DAB, DD B). In the second embodiment, the selector is provided between one bus of the second CPU and the bus connected to the first CPU. Is also good. In this case, the configuration is the same as that of the first embodiment in which the instruction storage device and the data storage device are replaced with one dual-port memory.

Next, a third embodiment will be described with reference to FIG. In the third embodiment, the storage device in the accelerator (AC) has three memory ports including an address terminal for inputting an address and a data terminal for inputting and outputting data. It is characterized by using triple port memory (TPM). Although this tri-port memory is sometimes called a three-port memory, the same RAM space is allocated to the first memory port (P 1), the second memory port (P 2), and the third memory port (P It is a memory that can be accessed in parallel by the three ports in P3). In the third embodiment, as in the first and second embodiments, the first CPU (CPU 1) that performs host-like operation and the address bus (AB) connected to the first CPU are used. And a data bus (DB). Further, the accelerator radiator (AC) connected via these buses is connected to the second CPU (CPU 2) and the address bus (AB) and the data bus (DB). The control block (CTL), the instruction address bus (IAB) and the instruction data bus (IDB) connected to the second CPU, and the second CPU and the logic block ( A data address bus (DAB) and a data bus for data (DDB) connected to the BLK) and the triple port memory (TPM) described above are formed. As described above, the triple-port memory (TPM) of the third embodiment has three memory ports, so that each bus can be connected. Specifically, the first memory port (P 1) of the triple port memory includes: The address bus (AB) connected to the first CPU and the data bus (DB) are connected, and the second memory port (P2) has the instruction address connected to the second CPU. The bus (IAB) is connected to the instruction data bus (IDB), and the third memory port has a data address bus (DAB) and a data bus (DDB) connected to the second CPU. And are connected. Therefore, there is no need to provide a selector that was required in the first and second embodiments. That is, the control block (CTL) does not require the signal lines connected to the control block and the selector described in the first and second embodiments. Further, the setting of the first bit (1 bit) of the control register for controlling the selector described in FIG. 2 is not required. The configuration of the logic block (BLK) is not particularly limited, but there is no problem even if the configuration is the same as that shown in FIG.

The operation of the third embodiment will be described below. First, the host CPU 2 transfers a program in which instructions and data for the accelerator CPU 26 are mixed to the triple port RAM 50. Next, similarly to the first embodiment, the accelerator CPU 26 is activated, and the accelerator CPU 26 fetches the instruction of the triple port RAM 50 and starts the operation.

In the third embodiment, the address bus (AB) and the data bus (DB) connected to the first CPU (CPU 1) and the instruction address connected to the second CPU (CPU 2) The dress bus (IAB) and the instruction data bus (IDB) are the first memory port (PPM) of the triple port memory (TPM), respectively.

1) and the second memory port (P 2), the selector 1 (S E L 1) and the selector 2 (S E L) required in the first and second embodiments.

2) is not required. This has the advantage that control is simplified. In the third embodiment, when the second CPU (CPU 2) is operating, the first CPU (CPU 1) issues an instruction or data or an instruction and data from the first CPU (CPU 1). Can be transferred through the first memory port (P 1) of the triple port memory. Therefore, when it is desired to operate a different program, it is possible to transfer the next program while operating the previous program, thereby reducing the processing overhead and improving the performance of the entire information processing device. Can be increased.

Next, a fourth embodiment will be described with reference to FIG. The fourth embodiment is a modification of the second embodiment using the dual port memory described above. In the fourth embodiment, the fifth selector (SEL5) for switching between the lower bit and the upper bit is provided on the instruction data bus of the second CPU (CPU2) in the accelerator (AC). It is unique. The second CPU (CPU 2) of the fourth embodiment has an instruction length of 16 bits and an operation bit length of 32 bits. On the other hand, the bit width of the dual port memory (DPM) is 32 bits. Therefore, the second CPU accesses the dual-port memory with the instruction bus (IAB, IDB) and the data bus (DAB, DDB) with 32 bits. Therefore, the fifth selector (SEL5) receives the information of the instruction address bus (IAB) output from the second CPU, and converts the 32-bit instruction data output from the dual port memory (DPM). Select the required upper 16 bits or lower 16 bits and output it to the second CPU.

As described above, in the fifth embodiment, the dual-port RAM can be used even when the bit length of the instruction is different from the bit length of the data.

FIG. 9 illustrates a fifth embodiment. The fifth embodiment is also a modification of the second embodiment using the dual port memory described above. This embodiment In 5, the data bus of the second CPU (CPU 2) in the accelerator (AC) has a sixth selector (SEL 6) that switches between lower and upper bits. There is a feature. The second CPU (CPU 2) of the fifth embodiment has an instruction length of 16 bits and an operation bit length of 32 bits. On the other hand, the bit width of the dual port memory (DPM) is 32 bits. For this reason, the second CPU accesses the dual-port memory with the instruction bus (IAB, IDB) and the data bus (DAB, DDB) with 32 bits. Then, the fifth selector (SEL 5) receives the address information output from the second CPU and selects the necessary upper or lower 16 bits from the accessed 32 bits. Output. As described above, in the fifth embodiment, even when the bus width of the instruction bus and the bus width of the data bus are different, the dual-port RAM can be used. In the above, the system configuration of the host ァ ρ and the accelerator was explained. However, there is no problem if the host CPU and accelerator are configured on the same chip. The instruction storage device (IM) and the data storage device (DM) of the first embodiment, the dual-port memory (DPM) of the second, fourth, and fifth embodiments, and the triple-port memory (TPM) of the third embodiment PM) may be composed of flash memory. As a result, data can be retained even when the power supply is stopped, so that when the power supply is restarted, it is possible to reproduce the same state as at the end of the previous time.

Claims

The scope of the claims

1. An information processing device having a first central processing unit, a second central processing unit, and a storage device,

The first central processing unit outputs an instruction and data to the storage device via the same bus,

The information processing device, wherein the second central processing unit accesses the storage device via an instruction bus and a data bus.

2. In Claim 1,

The information processing device, wherein the first central processing unit transfers the program executed in the second to the storage device via the same bus.

3. In Claim 1,

A selecting circuit for selectively connecting the same bus and the instruction bus to the storage device; and selectively connecting the same bus and the data bus to the storage device. An information processing apparatus, further comprising: a selection circuit for performing the operation.

4. In Claim 1,

The storage device is a dual-port memory,

A first port of the dual-port memory is selectively connected to the same bus and the instruction bus via a selection circuit;

The information processing apparatus according to claim 2, wherein a second port of the dual port memory is connected to the data bus.

5. In Claim 1,

The storage device is a dual-port memory,

A first port of the dual port memory is selectively connected to the same bus and the data bus via a selection circuit; The information processing apparatus according to claim 1, wherein a second port of the dual port memory is connected to the instruction bus.

6. In any one of claims 1 to 5,

The information processing apparatus, wherein each of the same bus, the instruction bus, and the data bus includes a bus to which an address is transferred and a bus to which data is transferred.

7. a first central processing unit;

A first bus connected to the first central processing unit for transferring instructions and data;

A second central processing unit;

A second bus connected to the second central processing unit and transferring instructions; and a third bus connected to the second central processing unit and transferring data.

A storage device;

A first selection circuit that is connected to the first bus and the second bus, and selects the first bus or the second bus and connects the selected bus to the storage device;

A second selection circuit that is connected to the first bus and the third bus, and selects the first bus or the third bus and connects the selected bus to the storage device. An information processing apparatus characterized by the above-mentioned.

8. In Claim 7,

The storage device has a first memory for storing instructions and a second memory for storing data.

The information processing apparatus according to claim 1, wherein the first selection unit is connected to the first memory, and the second selection unit is connected to the second memory.

9. In Claim 7,

The storage device is a dual-port memory;

The selecting means is connected to a first memory port of the dual port memory,

The information processing apparatus according to claim 2, wherein said second selecting means is connected to a second memory port of said dual port memory.

10. A first central processing unit;

A second central processing unit;

A second bus connected to the second central processing unit;

A third bus connected to the second central processing unit;

A storage device having a first memory port and a second memory port, connected to the first bus and the second bus, and selecting the first bus or the second bus; A first selection circuit connected to the first memory port of the storage device by

The information processing device according to claim 3, wherein the third bus is connected to a second memory port of the storage device.

1 1. In claim 10,

The second bus is a bus to which instructions are transferred;

The information processing device, wherein the third bus is a bus to which data is transferred.

1 2. In claim 11,

The second bus is a bus to which data is transferred;

The information processing device, wherein the third bus is a bus to which instructions are transferred.

13. In any one of claims 7 to 12, wherein each of the first bus, the second bus, and the third bus includes a bus to which an address is transferred and a data. An information processing device comprising a bus to be transferred.

14. A first central processing unit having a Neumann architecture, and a c-processor for processing a program transferred by the first central processing unit.

—An information processing apparatus comprising a second central processing unit having a bird architecture.

15. In claim 14,

The first central processing unit is connected to a storage device via a first bus,

The information processing apparatus according to claim 1, wherein the second central processing unit is connected to the storage device via a second bus and a third bus.

16. In claims 14 or 15,

The information processing apparatus according to claim 1, wherein the storage device is a dual-port memory having a first memory port and a second memory port.

1 7. In claim 16,

The information processing device includes a selection circuit that selectively connects the first bus and the second bus to the first memory port,

The information processing device according to claim 1, wherein the third bus is connected to the second memory port.

18. In Claim 16,

A first selection circuit that selectively connects the first bus and the second bus to the first memory port; the first bus and the third bus; And a second selection circuit for selectively connecting the second memory port to the second memory port.

19. In Claims 14 or 15, wherein the storage device has a first storage device for storing instructions and a second storage device for storing data,

The information processing apparatus further includes: a first selection circuit that selectively connects the first bus and the second bus to the first storage device; the first bus and the second bus. An information processing apparatus, comprising: a second selection circuit that selectively connects the third bus to the second storage device.