WO1990002993A1

WO1990002993A1 - Electronic device for memorizing digital data e.g. of a key input sequence

Info

Publication number: WO1990002993A1
Application number: PCT/GB1989/001079
Authority: WO
Inventors: Stephen Donald Broome
Original assignee: Star Microterminals Limited
Priority date: 1988-09-15
Filing date: 1989-09-14
Publication date: 1990-03-22

Abstract

An electronic device for memorizing and recalling key stroke sequences is connectable between a computer and its keyboard. The device has a microprocessor (17) controlling memorization of the sequences in a memory (18) at addresses specified via a key pad (1). The microprocessor is connected by two monitor and drive circuits (21, 22) to the clock and data lines (4c, 4d, 3c, 3d), between the computer and its keyboard. Between these circuits is a switch (23) for disconnecting the keyboard during transmission of a memorized keystroke sequence.

Description

Electronic device for memorizing digital data, e.g. of a key input sequence.

Field of the Invention

The present invention relates to an electronic device fo memorizing digital data signals in particular, though not exclusively, for use with a computer having a keyboard. Background of the Invention

Frequently in use of a computer, for instance during wor processing at the end of a letter, a particular string of keystrokes is used repeatedly in different operations. It is convenient if this string of keystrokes can be memorized for use on demand whenever required. This facility is available with certain software. However if the particular software in use at the time does not have the facility to memorize string of keystrokes, then every time the strings are required they must be made manually. The Invention T e object of the invention is to provide a stand alone device which can function as a key stroke memory and is adapte for use with a computer and keyboard without modification of either.

According to the invention there is provided an electroni device for memorizing digital data signals comprising:- input connection means for receiving digital data signals output connection means for transmitting digital data signals; processor means including a memory for remembering and reproducing for transmission at least one digital data signal; the input connection means, the output connection means and the processor means being connectable for:- (i) passage of digital data signals from the input connection means to the output connection means (and vice versa), (ϋ) passage of digital data signals from the input connection means to the processor means for memorization in the memory, and

(iii) passage of a memorized digital data signal from the processor means to the output connection means for transmissi from the output connection means; and a manually operable control for causing the processor means to memorize a specified digital data signal in the memo and for causing the processor means to transmit a memorized digital data signal from the memory. For use with a computer and its keyboard, the input connection means is a connector complementary to an output connector of the keyboard, and the output connection means is connector complementary to the computer's keyboard input connector. Thus the keyboard is connected to the computer vi the device of the invention. The digital data signals to be memorized will be keystroke sequences.

The device may be arranged to be transparent at all tim to signals being sent from the keyboard to the computer. Th device preferably includes a normally closed switch between t input connection means and the output connection means for isolating the output connection means from the input connecti means under control of the processor means during transmissi It will not normally be necessary for the switch to be open during a process of memorization of a keystroke sequence, si with the switch closed such a sequence can then be utilized both directly in the computer and by the memory means for memorization. However it is envisaged that the switch may b arranged to be open during memorization.

Preferably the device includes an input monitor and dri circuit on input clock and data lines between the input connection means and the switch, and an output monitor and drive circuit on output clock and data lines between the out connection means and the switch, enabling the signals coming from the keyboard to the device (and indeed the signals comi from the computer to the device) to be monitored for memorization thereof and driving the output to the computer during transmission of a memorized signal.

Conveniently the device is adapted to draw power for its operation from the computer via the output connection means. Whilst the device may be adapted to operate uniquely with computers utilizing a particular keyboard/computer communication protocol, the device is preferably adapted on first use with a computer to memorize the protocol associated with digital data signal transmission to and from the computer and to transmit memorized signals in the memorized protocol.

The device preferably includes a micro-computer controlle by software stored in a PROM. The memory for the signals and their protocol parameters is preferably a non-volatile RAM. For optimum use of the RAM, dynamic memory management techniques can be employed.

Whilst the switch will normally be open during reproduction of a keystroke sequence, the device may be arranged to recognise specific keystrokes, for instance one representative of an abort signal, if the incorrect memorized signal is being reproduced.

To help understanding of the invention two specific embodiments thereof will now be described with reference to th accompanying drawings, in which:- The Drawings Figure 1 is a top view of an operating panel of a device of the invention;

Figure 2 is a diagrammatic view of the device connected between a keyboard and a computer;

Figure 3 is a block diagram of the main operational components of the device;

Figure 4 is an operational flow chart for the device; and Figure 5 is a view similar to Figure 1 of another device of the invention. The Preferred Embodiment The device has a keypad 1 set on a housing 2. Two cables 3,4 are provided, one 3 terminating in a connector 5 plugged into the receptacle 6 of a computer 7 - into which receptacle the connector 8 of the keyboard 9 is normally plugged. The other lead 4 terminates in a connector 10 into which the keyboard connector 8 is plugged.

The keypad 1 has twenty serially numbered keys 11. The keypad is recessed slightly in the housing 2 to enable a markable over-lay to be placed on the key pad to identify specific keystroke sequences associated with the specific keys. The device also has two further keys, a SAVE key 12 and a LEAR key 13. Further it has three LED indicators, "learn" 14, "power" 15 and "error" 16.

Shown in the block diagram. Figure 3 is a central microprocessor 17 having its own internal PROM memory 17'. Peripherally connected to the microprocessor are the keypad 1, a lithium battery powered RAM memory 18 having its own lithium battery enabling it to remember its memorized data when the computer is switched off (the computer being the normal source of power for the device), the LED indicators 14,15,16, a clock 19, and a reset circuit 20. The microprocessor 17 communicate with the keyboard 9 and computer 7 by respective "input" and "output" monitor and drive circuits 21,22. These enable the microprocessor to both monitor the signals on the clock and data lines 3 , 3_d, 4 , 4- of the cables 3,4 and pass signals thereto. The lines 3_c and 4_c and 3, and 4, are normally connected by a normally closed switch 23. This is an electronic switch under control of the microprocessor.

Signals are passed on to the clock and data lines from th keyboard 9 to the computer 7 in accordance with a protocol which is standard to the particular model of computer. Essentially the clock line passes a burst of pulses for each character corresponding to a keystroke, the data line passes a synchronous burst of pulses. These may be on or off in synchronism with certain of the clock pulses to indicate the specified character. Different protocols employ different numbers of bits, i.e. data pulses, typically 8 or 10; differe pulse widths within a burst; different pulse spacings within burst, typically of the order of 60 microseconds.

Referring now to Figure 4, on initial connection of the device for the first time, the reset circuit 20 initiates the microprocessor 17. This under control of the software in its PROM 17', on first use of the keyboard 9, monitors the clock and data lines 4 , 4_d to measure the protocol of the characte transmission and memorize the features of the protocol in the RAM 18. It should be noted that for learning the protocol an indeed for learning the character sequence to be reproduced, is unnecessary for the microprocessor 17 to interpret the characters, since it is merely required at the appropriate ti to reproduce the characters - comprised of their original bit - in their original form.

As soon as the protocol has been memorized, the device i ready to "learn" a keystroke/character sequence. For this th LEARN key 13 on the device is depressed and the computer's keyboard 9 is used to send to the computer 7 the sequence to memorized. This is monitored by the monitor portion pf the input circuit 21 and passed by the microprocessor to the RAM 18. At the end of the sequence the SAVE key 12 on the device is depressed followed by one of the numbered keys 11. This action associated this number with the just memorized sequenc in addition, at any point in this process one of the previous programmed keys may be depressed to send its sequence to the computer, and this sequence will then be incorporated as part of the new sequence.

For reproduction of this sequence and sending of it from the device to the computer 7, the numbered key 11 is depresse without either of keys 12, 13 having been preliminarily depressed. Initially this action causes the microprocessor 1 to open the switch 23 (which was closed during the learning steps to enable the keyboard to send to the computer). This opening of the switch 23 disconnects the lines 3 , 3- from th line 4 , 4,. The microprocessor 17 then reproduces the characters of the required sequence in accordance with the memorized protocol features appropriately timed by the clock and the memorized data bits, and causes the driver portion of the circuit 22 to send the character sequence on the lines 3 , 3_fl to the computer 7 for use. The switch 23 is not open throughout transmission of a character sequence, but is opened only whilst a character is being sent. This is, for instance, to avoid the keyboard reacting to the characters as they are sent. The switch is closed between character transmissions to permit, for instance, capital-lock-light illumination by a signal from the computer to the keyboard. Once the required sequence has been reproduced and sent to the computer, the switch 23 is closed for normal operation of the keyboard. If the key stroke buffer in the computer becomes full, the computer inhibits the sending of further information by holdin clock line -low for instance. The device will monitor this in the same manner as a conventional keyboard and will suspend sending of the sequence until the condition is removed. if a fresh sequence is to be remembered in place . f an earlier one, the earlier one is replaced by the fresh sequence which latter is assigned to the corresponding key. Further Embodiment

Referring now to Figure 5, the device there shown is similar to that of Figure 1, as regards features bearing the same references with the addition of two further keys - a PAUS key 51 and PAGES key 52.

In use to memorize a keystroke sequence requiring a computer to pause, as for retrieving information from disk, th PAUSE key is depressed at the appropriate point in the sequenc whilst it is being memorized. This causes a code recognizable by the device's microprocessor to be memorized in the sequence When the latter is sent from the memory, the microprocessor causes a pause in the transmission at this point in the sequence. The device of Figure 1 has a memory having twenty addresses. This can be limiting. The device of Figure 5 has a four hundred address memory. The individual addresses are accessed, for learning and sending of keystroke sequences, by first depressing the PAGES key followed by one of the pad keys 11. This operation identifies a selected one of twenty "pages of memory addresses. Next the particular address within the page is selected by depressing the appropriate pad key. The key pad has a transparent plastic overlay sheet 53 fixed t the body of the device at the upper side of key pad. Beneath this sheet is a paper overlay 54 on which is printed a grid associated with the pad keys 11. Information identifying the sequences for the particular memory page can be written on the grid at the keys' positions. Correct alignment of the paper overlay 55 is ensured by aligning arrows 56 printed on it with arrows 57 printed on the body of the device. Both overlay sheets 53, 54 being thin and flexible, depression of the pad keys through them is not interfered with.

It should be particularly noted that the above described devices of the invention memorize the entire key stroke sequences, without decoding them in any way. The sequences ar memorized in the digital form of each and every key stroke in the devices' memory.

Claims

1. An electronic device for memorizing digital data signals comprising:- input connection means for receiving digital data signals output connection means for transmitting digital data signals; processor means including a memory for remembering and reproducing for transmission at least one digital data signal; the input connection means, the output connection means and the processor means being connectable for:- (i) passage of digital data signals from the input connection means to the output connection means (and vice versa), (ii) passage of digital data signals from the input connection means to the processor means for memorization in the memory, and

(iii) passage of a memorized digital data signal from the processor means to the output connection means for transmissio from the output connection means; and a manually operable control for causing the processor means to memorize a specified digital data signal in the memor and for causing the processor means to transmit a memorized digital data signal from the memory.

2. An electronic device as claimed in claim 1, including a normally closed switch between the input connection means and the output connection means for isolating the output connectio means, from the input connection means under control of the processor means during transmission of a memorized digital dat signal.

3. An electronic device as claimed in claim 2, wherein the switch is arranged to be open during transmission of individua signals in a seqence thereof and closed therebetween.

4. An electronic device as claimed in claim 2 or claim 3, including input clock and data lines between the input connection means and the switch, an input monitor and drive circuit on the said input lines between the input connection means and the switch for passing digital data signals from the input connection means to the processor means, output clock and data lines between the switch and the output connection means, and an output monitor and drive circuit on the said output lines between the output connection means and the switch for passing memorized digital data signals from the processor means to the the output connection means.

5. An electronic device as claimed in any preceding claim, wherein the input connection means is a connector complementary to an output connector of a computer keyboard, and the output connection means is a connector complementary to the computer's keyboard input connector.

6. An electronic device as claimed in claim 5, wherein the device is adapted to draw power for its operation from the computer via the output connection means.

7. An electronic device as claimed in any preceding claim, wherein the manually operable control comprises a.numeric keypad for identifying memory addresses at which digital data signals are to be memorized, and at least one key for _^ instructing the processor means to memorize a digital data signal.

8. An electronic device as claimed in claim 7, wherein two keys are provided for instucting the processor means to memorize a digital data signal, a first key to initate memorization at the begining of the signal and a second key to terminate memorization at the end of the signal.

9. An electronic device as claimed in claim 7 or claim 8, including a key for inserting a code in the memorized digital data sequence at which a pause is to occur when the signal is transmitted, the processor means being adapted to pause the transmission at the position of the code.

10. An electronic device as claimed in claim 7, claim 8 or claim 9, wherein a plurality of memory addresses are associated with each pad key, and the device includes a key for identifying - in combination with a corresponding pad key - on of the said plurality to be selected.

11. An electronic device as claimed in any preceding claim, the device being adapted on first use with a computer to memorize the protocol associated with digital data signal transmission to and from the computer and to transmit memorize signals in the memorized protocol.

12. An electronic device as claimed in claim 11, including a reset circuit which, on connection of the device to the computer, causes the device to memorize the computer's protoco in the memory.

13. An electronic device as claimed in any preceding claim, wherein the processor means comprises a micro-computer controlled by software stored in an associated PROM and a RAM for storing digital data signals.

14. An electronic device as claimed in any preceding claim, wherein the device is so adapted that a particular command given to the processor means via the manually^" operable control causes the device to abort transmission of a memorized signal presently being transmitted. _^

15. An electronic device as claimed in any preceding claim, wherein the device is adapted to suspend memorized signal transmission in the event of it receiving a signal at the output connection means indicative of a buffer being transmitted to being full.

16. An electronic device as claimed in claim 7 or any one of claims 8 to 15 as appendant to claim 7, in combination with an overlay for the keypad for identifying the contents of memory addresses associated with particular keys of the pad.