US20050077941A1

US20050077941A1 - Selectable delay pulse generator

Info

Publication number: US20050077941A1
Application number: US10/961,584
Authority: US
Inventors: John Fagan; Mark Bossard
Original assignee: Atmel Corp
Current assignee: Atmel Corp
Priority date: 2003-10-10
Filing date: 2004-10-08
Publication date: 2005-04-14
Also published as: WO2005036747A3; US8193846B2; EP1673862A2; TW200520388A; CN1951010A; WO2005036747A2; US20090284296A1

Abstract

A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from provisional application No. 60/510,748 filed Oct. 10, 2003.

TECHNICAL FIELD

The present invention relates to a pulse generator having selectable delays between pulses. The selectable delays provide a pulse train output.

BACKGROUND ART

Programmable delay circuits have been used in a variety of applications, for example, in testing and in memory configurations. A variety of digital designs and techniques are available for controlling the delay steps and pulse widths of an output signal. Prior art circuits suffer from the disability to quickly switch a delay from the clock chain for accuracy or precise timing needs, or for pure data speed or throughput increase. For example, U.S. Pat. No. 5,594,690 to Rothenberger et al., entitled “Integrated circuit memory having high speed and low-power by selectively coupling compensation components to a pulse generator,” Rothenberger describes a major problem with existing circuits not having predictable switching speeds, and large delay tolerances. An object of the Rothenberger invention is to provide faster operating speeds and smaller power dissipation. With the overall need to build faster circuits in a variety of areas, pulse generator designs must evolve and improve. This requirement may be met by building faster digital devices or by implementing new design ideas to reduce delay within any system that requires variable pulse outputs or variable pulse widths. A speed or throughput increase also provides an increase in bandwidth as the rate or density of data increases.

SUMMARY OF THE INVENTION

The present invention is a selectable delay pulse generator, which is designed to create a pulse train with a delay between pulses, or pulse edges, representing encoded data. The present invention significantly increases the bandwidth within a given clock cycle by utilizing a delay chain with taps fed to a reduced voltage pre-charge multiplexer using an automatic pre-charge control circuit. The multiplexer selects an output from the delay chain, and quickly switches the pulse generator output with the aid of a reduced voltage pre-charge circuit.
The delay chain is made of individual delay elements, where the speed of each element may be governed by a current mirror.
A multiplexer is coupled to and controlled by an n-bit register that is coupled to the output of a state machine. In general, the state machine output is determined by a transition function and the state of an input to the state machine. In some embodiments, the state machine 40 may include a counter, a state mapping function, and a plurality of output states. It is preferred that the state machine circuitry is implemented on the same IC (integrated circuit) with the other pulse generator circuits. However, the state machine may be implemented in hardware, for example an different integrated circuit, by software, or by other control signals.
Increased speed and, consequently, increased bandwidth, are due to a reduced delay through the reduced voltage pre-charge multiplexer and the relaxed timings allowed by the shortened pulses of the automatic pre-charge circuit. A minimum delay increment can be shorter in time, more encoded pulses per clock period, or a faster clock period, (or a combination) may be implemented and the encoding system can be faster.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of an exemplary embodiment of a delay pulse circuit.
FIG. 2 is a timing to diagram indicating the reduced delay time due to a reduced voltage pre-charge circuit of the exemplary pulse circuit of FIG. 1.
FIG. 3 is a timing diagram, indicating the reduced timing parameters in an encoded pulse train of the exemplary pulse circuit of FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

The exemplary selectable delay pulse generator 100 of FIG. 1 uses a delay chain 10 combined with a reduced voltage pre-charge multiplexer 20 with an automatic pre-charge circuit 60. This combination provides an increase in maximum bandwidth for encoded data within a given clock period of clock input 11. The use of a reduced voltage pre-charge significantly decreases the delay of the tap 12 to multiplexer output 70, allowing a state machine 40 controlling the selected taps more time to operate. Therefore, the pulse generator 100 is able to run at a higher speed or have a higher density of encoded data within a given clock cycle. The automatic pre-charge circuit 60 creates a short pulse output that additionally relaxes the timing requirements for the state machine 40.
A clock of known frequency is connected to the clock input 11 and to the delay chain 10. In a specific embodiment, the selectable delay pulse generator 100 consists of a current controllable delay chain 10 with a plurality of n output taps 12 (for example, 48 taps). An optimized delay chain will contain as many delay elements to provide as many delay intervals as possible with in a single clock period. Generally, the delay chain provides rising or falling edges at regular selectable intervals. In one embodiment, the delay chain is a current controlled delay. The delay chain 10 is made of individual delay elements, where the speed or delay interval of each element may be controlled, for example by an ADC (analog-to-digital converter) driven current mirror. Also, in another embodiment, a control loop may be used to set the current mirror, for example from between 10-100 microAmps, therefore setting the delay chain speed. Adjusting the delay chain speed may be used to calibrate the delay chain delay to an external clock. In addition, adjusting the delay chain speed may be used to counter act variations in process, temperature, or voltage. The output taps 12 coupled to the delay chain 10 are selectable by a pre-charge multiplexer 20 having individual (tap) selects 14 for each output tap 12. The output taps 12 are controlled by an n-bit register 30.
A delay between pulses output by the pulse generator 100 is a function of the data to be encoded by the state machine 40. Generally, the state machine 40 receives the data to be encoded, determines the next tap to be selected, and selects the tap when triggered. The encoding method depends on the encoding scheme. An exemplary encoding scheme is shown in the chart below (where T is the current tap number):

Data In Delay Next Tap Selection (2 ns per tap)

00 4 ns T + 2

01 6 ns T + 3

10 8 ns T + 4

11 10 ns T + 5
The actual pulse is created by the rising edge of the clock input 11 moving through the delay chain 10 as it is observed through the output taps 12, which shift as the clock moves through the delay chain 10. The state machine 40, controlling the pre-charge multiplexer 20 through a register 30 having a pre-selected number of bits, couples at least one output tap 12 to the encoded output line 50, to define the time location of critical signal edges (rising or falling) of the encoded pulse train output. In one embodiment, the encoded pulse train output is provided to the input of the state machine 40, which is then triggered to change its state and select a new output tap 12. The state machine 40 must be able to select or couple the new output tap to the encoded output 50 before the clock edge that propagates through the delay chain 10 reaches the new output tap 12 that is to be selected. The minimum encoded delay time increment must be greater than the amount of time it takes for the output tap signal edge to travel from the output tap 12 to the encoded output line 50, in addition to the amount of time it takes for the state machine 40, tap register 30, and pre-charge multiplexer 20 to select the next output tap 12.
Referring to FIGS. 1 and 2, a novel feature of the pulse generator is the reduced voltage pre-charge multiplexer 20 having an automatic pre-charge circuit 60 operating at a lower voltage V_pcthan the supply voltage V_dd. The reduced voltage pre-charge of the multiplexer reduces the above mentioned time delay and allows the to operate faster. For example V_pc=1.8 volts when used with a supply voltage V_dd=2.85 volts. The automatic precharge circuit 60 uniformly completes each pulse started by the signal on the selected output tap. In an exemplary embodiment, the pre-charge circuit 22 is coupled to a pre-charge control 61. The pre-charge control 61 is also coupled to the encoded output 50 of the state machine. In one embodiment the pre-charge control 61 delay is the encoded output signal to define the pulse width (310 in FIG. 3) of the encoded output 50. In an alternate embodiment, the pre-charge control 61 may dynamically adjust the pulse width.
The reduced voltage pre-charge circuit allows a faster switch point 210 due to the reduced voltage of V_pcthus providing a reduced switch delay time from a selected output of tap 12 to the multiplexer output 70. The reduced switch delay time relieves the state machine 40 from having to complete the entire duration of each pulse before starting the next output tap 12 selection. The faster the output is generated from the delay chain 10 edge at the output tap 12, the faster the state machine 40 will be triggered to shift into the next select state. The circuit provides the following advantages:
1. A reduced delay time 210, as shown in FIG. 2, from a selected output tap 12, through the multiplexer 20 allowing more time for the state machine 40 to process new data and switch to a next state. This shortened delay time allows using a smaller pulse width 310, as shown in FIG. 3, as the minimum encoded value on encoded output 50 allows for greater bandwidth savings (i.e., more pulses per period).
2. A short pulse 310, as shown in FIG. 3, is generated at the encoded output 50 instead of simply routing out the selected output tap, thereby relaxing the timing requirements on the tap-selecting state machine 40.
In an exemplary resulting output, as shown in FIG. 3, the pulse generator 100 encodes data into a pulse stream having pre-selected separations between each pulse. When a selected tap is routed through the multiplexer, the output of the delay chain/multiplexer would be a rising consists of edge 305 of a delayed clock edge. The output would stay high until the next state change. The multiplexer output state needs to change quickly enough (e.g., within a cycle 330) to select the next desired output tap from tap₁to tap_nof the propagation delayed clock edge. The multiplexer output must complete a prior state switch, for example, well before the next desired state change 350 reaches output tap_xin the delay chain. In this diagram, the multiplexer has switched quickly enough to allow a falling edge within the time period 310. The multiplexer delay also allows a proper setup time 340 before the next desired rising edge 350. This would introduce a set up requirement equal to the minimum allowed low pulse on a flip-flop's clock (not shown).
By having the multiplexer output a short pulse 310 by utilizing an automatic pre-charge circuit, a minimum pulse width is allowed and the state machine 40 does not need to account for a longer set-up time. The exemplary selectable delay pulse generator effectively has a substantially reduced set-up time requirement between a tap selection and the clock edge arriving at the output tap to be selected.
It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading an understanding the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which said claims are entitled.

Claims

1. An electronic device for producing a plurality of pulses having a selectable delay between each pulse comprising:

a signal delay chain having a plurality of taps;

a plurality of tap select devices coupled to said plurality of taps; and

a tap select register coupled to said plurality of tap select devices, said tap select register configured to selectively couple at least one of said plurality of delay chain taps to a reduced voltage pre-charge circuit.

2. The electronic device of claim 1, wherein said signal delay chain is coupled to a clock signal.

3. The electronic device of claim 1, wherein said signal delay chain is a current controlled delay chain.

4. The electronic device of claim 1, wherein said reduced voltage pre-charge circuit is coupled to a pre-charge control circuit.

5. The electronic device of claim 1, wherein said tap select register is coupled to a state machine.

6. An electronic device for producing a selectable delay pulse width, said delay between pulses representing encoded data, comprising:

a current controlled delay chain, said delay chain having a plurality of taps;

a reduced voltage pre-charge multiplexer coupled to at least one of said plurality of taps; and

a tap select register coupled to said multiplexer, said tap select register configured to couple said delay chain to said multiplexer.

7. A method for producing an encoded pulse train having a selectable delay between each pulse comprising:

applying a clock signal to a delay chain;

selecting at least one delayed clock signal from the delay chain; and

applying a reduced voltage pre-charge signal to the selected delayed block signal, thereby decreasing the output delay time of said selected delayed clock signal.

8. The method of claim 7, wherein said selectable signal delay is a achieved by controlling a current delay chain.

9. The method of claim 7, wherein said selecting a delayed clock signal from the delay chain is performed by a multiplexer.

10. The method of claim 9, further comprising controlling the multiplexer by a register coupled to a state machine.