1363949 101年.02月日桉正翻 六、發明說明： 【發明所屬之技術領威】 _]本發明係關於4電腦主機板，尤指—種可彈性支持雙 倍資料速率2 (Double Data Rate 2，簡稱DDR2)記憶 體及雙倍資料速率3 (Double Data Rate 3 ’簡稱. DDR3)記憶體之主機板。 【先前技術】 [0002] 習知之個人電腦主機板上，除了有中央處理器，控制晶 片組及可供安裝外接卡之插槽外’還有複數用於安裝記 憶體之連接器。用戶可以根據需要’安裝不同數量之記 憶體。隨著記憶體製造技術之快速發展，DDR3記憶體因 其在功耗及速度方面更強之性能將成為未來動態隨機存 取記憶體之主要潮流。然而，從目前普遍使用之DDR2記 憶體轉換至DDR3記憶體仍需要一定之過渡期。 [0003] 惟，由於DDR2和DDR3記憶體之操作電壓不同，DDR2記憶 體之操作電壓為VDD = 1. 8V，VTT = 0. 9V，而DDR3記憶體 # 之操作電壓為VDD = 1. 5V，VTT=0· 7SV。因而，p前在主 機板之設計上，仍無一款主機板可同時支持DDR2及DDR3 記憶體。因此，如何提供一種電腦主機板，可支持不同 規格之記憶體，即為業界急需解決之課題。 【發明内容】 [0004] 繁於以上内容，有必要提供一種可彈性支持不同類型記 憶體之主機板。 [0005] 一種支持混合式記憶體之主機板，包括一第一連接器、 一第二連接器及一與該第一連接器及該第二連接器連接 09613249^單編號Α_ 第3頁/共1〇頁 1013067858-0 1363949 101年02月22日 之電壓調節電路，該第一連接器用以安裝一第一類型記 隐體’ β亥第二連接器用以安裝—第二類型記憶體，當該 第一或第二類型記憶體被安裝於與其對應之連接器時， 該文裝有對應記憶體之連接器產生一識別訊號，該電壓 調節電路根據該識別訊號判別被安裝在該主機板上之記 憶體類型，並為該類型之記憶體提供適合之工作電壓。 ^)006]上述支持混合式記憶體之主機板可自動偵測安裝在該主 機板上之記憶體類型，並透過電壓調節電路提供適合之 電壓’使同-主機板可彈性支持不同類型之記憶體，滿 足不同用戶之需求。 【實施方式】 [0007]參考圖1，本發明支持混合式記憶體之主機板之較佳實施 方式包括一電麼調節電路1〇、一第一連接器2〇及一第二 連接器30。該第一連接器20為一用來安裝DDR2記憶體之 DDR2連接器，該第二連接器3〇為一用來安裝j)DR3記憶體 之DDR3連接器，同一時間在該主機板上只能選擇安裝— 種類型之記憶體。 [0008] 該電壓調節電路10包括一控制器12、—濾波器14、一線 性穩壓器16及一回授偏壓電路18。 [0009] 該回授偏壓電路18包括兩個場效應電晶體〇1和〇2及五個 電阻R1~R5。該場效應電晶體Q1和Q2均為NMOS場效應電 晶體’該場效應電晶體Ql及Q2之閘極分別與該第一連接 器20及第二連接器30之一接地引腳連接，該場效應電晶 體Q1之閘極還透過該電阻R1與一 5V電源連接，該場效應 電晶體Q1之源極接地，該場效應電晶體Q1之汲極與該場 0961324#單编號 AQ1(H 第 4 頁 / 共 1()頁 1013067858-0 1363949 101年.02月22日核正替換頁j 效應電晶體Q2之閘極連接並透過該電阻R2與該5V電源連 接’該場效應電晶體Q2之源極接地，該場效應電晶體Q2 之汲極透過該電阻R3與該控制器12之一回授引腳連接， 該回授引腳透過該電阻R4接地並與該電阻R5之一端相連 [0010] 該控制器12之輸出端與該濾波器14.之輸入端連接以傳輸 一電壓訊號，該濾波器14之輸出端輸出一濾波後之電壓 VDD，該濾波器14之輸出端與該回授偏壓電路18之電阻 R5之另一端連接以構成回授迴路，該濾波器14還將電壓 VDD傳送給該線性穩壓器16，並經該線性穩壓器16轉換為 電壓VTT分別提供給該第一連接器20及該第二連接器30。 該濾波器14之輸出端還直接與該第一連接器20及該第二 連接器30連接並向該兩連接器20、30輸出電壓VDD » [0011] 在本較佳實施方式中，該控制器12回授引腳端之回授電 壓Vfb設定為0.78V，該等電阻R卜R5之電阻值分別為 4.. 7千歐姆、4.7千歐姆、2. 4千歐姆、1. 2千歐姆及1. 1 千歐姆。 [0012] 當在該第一連接器20上安裝DDR2記憶體，該第二連接器 30空接，電腦系統開機時，該場效應電晶體Q1之閘極接 收該第一連接器20接地引腳產生之一低電平訊號，因此 該場效應電晶體Q1截止而場效應電晶體Q2導通，該電阻 R3接入回授電路，因為回授偏壓電路18必須將該控制器 12回授引腳端之回授電壓Vfb調整至控制器12回授引腳之 設定值0· 78V，根據回授電壓Vfb與輸出VDD之分壓公式 VDD=Vfb木（R5+RX)/RX，其中RX = (R3木R4)/(R3 + R4),計 09_产單编號A〇101 第5頁/共10頁 1013067858-0 1363949 101年.02月22日修正替換頁 算得該輸出電壓VDD為1. 8V，故控制器12將調整輪出電 壓，使濾波器14之輸出電壓VDD為1. 8V，該輸出電壓VDD 直接提供給該回授偏壓電路18及安裝在第一連接器2〇上 之DDR2記憶體，該輸出電壓vdd還透過線性穩壓器16轉 換成一VTT電壓（0. 9V)提供給DDR2記憶體。 [0013] 當在該第二連接器30上安裝DDR3記憶體，該第一連接器 20空接，電腦系統開機時，該場效應電晶體Q2之閘極接 收該第一連接器30接地引腳產生之一低電平訊號，因此 該場效應電晶體Q1導通而場效應電晶體Q2截止，因為該 | 回授偏壓電路18必須將該控制器12回授引腳端之回授電 壓Vfb調整至設定值〇. 78V ’根據回授電壓Vfb與輸出電 壓VDD之分壓公式VDD=Vfb*(R5+R4)/R4，計算得輸出電 壓VDD為1. 5V，故控制器12將調整輸出電壓，使濾波器 14之輸出電壓VDD為1. 5V，該輸出電壓VDD直接提供給該 回授偏壓電路18及安裝在第二連接器3〇上之DDR3記憶體 ，該輸出電壓VDD又透過線性穩壓器μ轉換成一νττ電壓 (0. 75V )提供給DDR3記憶體^ < [0014] 在該支持混合式記憶體之主機板上可選擇安裝不同類型 之記憶體，並根據該第一連接器2〇及該第二連接器3〇連 接後產生之接地訊號判別安裝在該主機板上之記憶體類 型，自動調整後向記憶體提供合適之·電壓值，在記憶體 換代時，尤其在DDR2記憶體轉換至DDR3記憶體之過渡期 内，為使用者提供更大之應用彈性。 [0015] 綜上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟，以上所述者僅為本發明之較佳實施例，舉凡 09613249^^« A〇101 第6頁/共10頁 1013067858-0 1363949 loi年.02月22日梭正替換頁 熟悉本案技藝之人士，在爰依本發明精神所作之等效修 飾或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 [0016] 圖1係本發明支持混合式記憶體之主機板較佳實施方式之 原理圖。1363949 101年.02月日桉正翻六, invention description: [Technology leader of the invention] _] The invention relates to 4 computer motherboards, especially one type of elastic support double data rate 2 (Double Data Rate 2, referred to as DDR2) memory and double data rate 3 (Double Data Rate 3 '. DDR3) memory motherboard. [Prior Art] [0002] On the personal computer motherboard of the prior art, in addition to the central processing unit, the control chip group and the slot for mounting the external card, there are a plurality of connectors for mounting the memory. Users can install a different number of memory as needed. With the rapid development of memory manufacturing technology, DDR3 memory will become the main trend of dynamic random access memory in the future due to its superior power consumption and speed. However, the transition from the currently widely used DDR2 memory to DDR3 memory still requires a certain transition period. [0003] However, due to the different operating voltages of the DDR2 and DDR3 memories, the operating voltage of the DDR2 memory is VDD = 1. 8V, VTT = 0.9 V, and the operating voltage of the DDR3 memory # is VDD = 1. 5V, VTT=0·7SV. Therefore, before the p-front design of the main board, there is still no motherboard that can support both DDR2 and DDR3 memory. Therefore, how to provide a computer motherboard that can support different specifications of memory is an urgent problem to be solved in the industry. SUMMARY OF THE INVENTION [0004] In the above, it is necessary to provide a motherboard that can flexibly support different types of memory. [0005] A motherboard supporting a hybrid memory, comprising a first connector, a second connector, and a first connector and the second connector are connected to the first connector and the second connector. 1〇 1013067858-0 1363949 The voltage regulating circuit of February 22, 101, the first connector is used to install a first type of hidden body 'beta second connector for mounting|the second type of memory, when When the first or second type of memory is mounted on the corresponding connector, the connector with the corresponding memory generates an identification signal, and the voltage adjustment circuit determines that the motherboard is mounted on the motherboard according to the identification signal. The type of memory and the appropriate operating voltage for this type of memory. ^) 006] The above-mentioned motherboard supporting the hybrid memory can automatically detect the type of memory installed on the motherboard, and provide a suitable voltage through the voltage regulating circuit to enable the same-board to flexibly support different types of memory. Body to meet the needs of different users. [Embodiment] Referring to FIG. 1, a preferred embodiment of a motherboard supporting a hybrid memory of the present invention includes an electrical adjustment circuit 1A, a first connector 2A, and a second connector 30. The first connector 20 is a DDR2 connector for mounting DDR2 memory, and the second connector 3 is a DDR3 connector for mounting j) DR3 memory, and can only be on the motherboard at the same time. Choose to install - the type of memory. The voltage regulating circuit 10 includes a controller 12, a filter 14, a linear regulator 16, and a feedback bias circuit 18. The feedback bias circuit 18 includes two field effect transistors 〇1 and 〇2 and five resistors R1 to R5. The field effect transistors Q1 and Q2 are both NMOS field effect transistors. The gates of the field effect transistors Q1 and Q2 are respectively connected to the ground pins of the first connector 20 and the second connector 30. The gate of the effect transistor Q1 is also connected to a 5V power supply through the resistor R1. The source of the field effect transistor Q1 is grounded, and the field effect transistor Q1 has a drain and the field 0961324# single number AQ1 (H number 4 pages / total 1 () page 1013067858-0 1363949 101. February 22 nuclear replacement page j effect transistor Q2 gate connection and through the resistor R2 connected to the 5V power supply 'the field effect transistor Q2 The source is grounded, and the drain of the field effect transistor Q2 is connected to a feedback pin of the controller 12 through the resistor R3. The feedback pin is grounded through the resistor R4 and connected to one end of the resistor R5 [0010] The output of the controller 12 is coupled to the input of the filter 14. to transmit a voltage signal. The output of the filter 14 outputs a filtered voltage VDD. The output of the filter 14 and the feedback The other end of the resistor R5 of the bias circuit 18 is connected to form a feedback loop, and the filter 14 is also The voltage VDD is transmitted to the linear regulator 16 and converted to a voltage VTT via the linear regulator 16 to the first connector 20 and the second connector 30. The output of the filter 14 is also directly Connecting with the first connector 20 and the second connector 30 and outputting a voltage VDD to the two connectors 20, 30. [0011] In the preferred embodiment, the controller 12 returns the pin end. The voltage Vfb is set to 0.78V, and the resistance values of the resistors R and R5 are respectively 4.. 7 kilo ohms, 4.7 kilo ohms, 2. 4 kilo ohms, 1.2 kilo ohms, and 1. 1 kilo ohms. When the DDR2 memory is mounted on the first connector 20, the second connector 30 is vacant, and the gate of the field effect transistor Q1 receives the ground pin of the first connector 20 when the computer system is turned on. a low level signal, so the field effect transistor Q1 is turned off and the field effect transistor Q2 is turned on, and the resistor R3 is connected to the feedback circuit because the feedback bias circuit 18 must return the controller 12 to the pin terminal. The feedback voltage Vfb is adjusted to the set value of the feedback pin of the controller 12 by 0·78V, according to the feedback voltage Vfb and the output VDD. Pressure formula VDD=Vfb wood (R5+RX)/RX, where RX = (R3 wood R4)/(R3 + R4), count 09_bill number A〇101 Page 5/10 pages 1013067858-0 1363949 The output voltage VDD is adjusted to 1. 8V, so that the controller 12 will adjust the output voltage so that the output voltage VDD of the filter 14 is 1. 8V, and the output voltage VDD is directly provided to The feedback bias circuit 18 and the DDR2 memory mounted on the first connector 2 are also supplied to the DDR2 memory by the linear regulator 16 to be converted into a VTT voltage (0.9 V). [0013] When the DDR3 memory is mounted on the second connector 30, the first connector 20 is vacant, and the gate of the field effect transistor Q2 receives the grounding pin of the first connector 30 when the computer system is turned on. A low level signal is generated, so the field effect transistor Q1 is turned on and the field effect transistor Q2 is turned off because the feedback bias circuit 18 must feedback the controller 12 to the feedback voltage Vfb of the pin terminal. Adjusted to the set value 〇. 78V 'According to the voltage divider formula VDD=Vfb*(R5+R4)/R4 of the feedback voltage Vfb and the output voltage VDD, the calculated output voltage VDD is 1. 5V, so the controller 12 will adjust the output. The voltage is such that the output voltage VDD of the filter 14 is 1.5 V. The output voltage VDD is directly supplied to the feedback bias circuit 18 and the DDR3 memory mounted on the second connector 3, and the output voltage VDD is again Converted to a ντ memory by a linear regulator μ to a voltage of νττ (0.75V) is provided to the DDR3 memory. [0014] A different type of memory can be optionally mounted on the motherboard supporting the hybrid memory, and according to the Grounding signal discrimination generated by a connector 2〇 and the second connector 3〇 The type of memory installed on the motherboard automatically adjusts to provide a suitable voltage value to the memory. When the memory is replaced, especially during the transition period of DDR2 memory to DDR3 memory, the user is provided with more Great application flexibility. [0015] In summary, the present invention complies with the requirements of the invention patent, and submits a patent application according to law. However, the above description is only a preferred embodiment of the present invention, such as 09613249^^« A〇101 page 6 / 10 pages 1013067858-0 1363949 loi year. February 22 shuttle replacement page familiar with the skill of the case Equivalent modifications or variations made by persons in accordance with the spirit of the invention are intended to be included within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0016] FIG. 1 is a schematic diagram of a preferred embodiment of a motherboard supporting a hybrid memory of the present invention.
【主要元件符號說明】 [0017] 電壓調節電路：10 [0018] 控制器：1 2 [0019] 遽波益· 14 [0020] 線性穩壓器：16 [0021] 回授偏壓電路：18 [0022] 第一連接器：20 [0023] 第二連接器30 [0024] 場效電晶體.Q1、 [0025] 電阻：R1〜R5 09613249产單編號 A〇101 第7頁/共10頁 1013067858-0[Main component symbol description] [0017] Voltage regulation circuit: 10 [0018] Controller: 1 2 [0019] 遽波益· 14 [0020] Linear regulator: 16 [0021] Feedback bias circuit: 18 [0022] First connector: 20 [0023] Second connector 30 [0024] Field effect transistor. Q1, [0025] Resistance: R1 to R5 09613249 Production order number A 〇 101 Page 7 / 10 pages 1013067858 -0