RU2526005C1 - Device to model schedule of enterprise employees work - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: device comprises a clock-pulse oscillator (CPO) 1, an enable trigger 2, a trigger of result availability 3, a group of counters 4₁, 4₂, …, 4_m, a matrix (m×n) of triggers 5₁₁, …, 5_mn, a matrix (m×n) of groups of the first AND elements 6₁₁, …, 6_mn, a group of the first summators 7₁, 7₂, …, 7_n, a group of the first registers 8₁, 8₂, …, 8_n, a group of the first comparison circuits 9₁, 9₂, …, 9_n, the second AND element 10, the second summator 11, the second comparison circuit 12, the group of second registers 13₁, 13₂, …, 13_m, the third register 14, a start inlet 15, an inlet of initial setting of a device 16, a group of the first outlets of a device 17₁, 17₂, …, 17_m, the second outlet of a device 18, the third outlet of a device 19, a group of the fourth registers 20₁, 20₂, …, 20_m, a group of the fifth registers 21₁, 21₂, …, 21_m, a group of the third comparison circuits 22₁, 22₂, …, 22_m.

EFFECT: increased reliability of a device and increased efficiency of a device.

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Description

The invention relates to computer technology and can be used to simulate work schedules of employees of the enterprise (workshop) with uneven loading at different time intervals (days of the week or month, with shift work during the day, etc.).

A device for modeling network graphs (SU No. 1383389 A1, IPC G06F 15/20, claimed 04.10.1986, published 03.23.1988, Bull. No. 11), containing a matrix of triggers, the first and second groups of triggers, the first and second groups of elements And , a group of counters, an AND element, a subtracting counter, a pulse generator, a group of delay elements, a group of OR-NOT elements, an AND-NOT element, an NOT element. The device arranges the vertices of the graph in accordance with the precedence rule.

The disadvantage of this device is the inability to simulate the work schedule of employees.

The reasons that impede the achievement of the technical result indicated below include the lack of funds that provide the ability to simulate the work schedule of employees.

A device is known for analyzing graph parameters (SU No. 1532942 A1, IPC G06F 15/20, announced December 3, 1986, published December 30, 1989, Bull. No. 48), comprising a multi-channel timer, multi-channel input-output unit, an array registration and comparison unit, channel number memory block, comparison block, first and second registers, delay elements, first and second blocks of OR elements. The device allows you to determine the value of the total resource consumed (the number of people, equipment and materials) for each moment of execution of the studied schedules.

The disadvantage of this device is the significant hardware costs.

The reasons that impede the achievement of the technical result indicated below include the lack of funds that provide the ability to simulate the work schedule of employees.

A device is known for solving the backpack problem (RU No. 2461060 C1, IPC G06F 17/00, G06F 7/00, announced May 25, 2011, published September 10, 2012, Bull. No. 25), containing a clock generator (GTI), a trigger trigger , result ready trigger, a group of m counters, groups of m first, second and third registers, fourth and fifth registers, groups of m sixth, seventh and eighth registers, ninth register, first and second adders, groups of m third and fourth adders , the first and second comparison circuits, a group of m third comparison circuits, an AND element, a device start input device, device reset input, first device output, a group of m second device outputs, third device outputs, fourth device outputs.

The disadvantage of this device is that the choice of option is carried out according to only one criterion - the maximum total cost of a filled backpack, as well as the impossibility of modeling the work schedule of employees.

The reasons that impede the achievement of the technical result indicated below include the lack of funds that provide the ability to simulate the work schedule of employees.

The closest device of the same purpose to the claimed invention in terms of features is a device for modeling the work schedule of employees of an institution (RU No. 2434273 C1, IPC G06F17 / 00, announced October 7, 2010, published November 20, 2011, Bull. No. 32 ), containing a clock generator 1, a group of counters 4 ₁ , 4 ₂ , ..., 4m, a matrix (m × n) of triggers 5 ₁₁ , ..., 5 _mn , a matrix (m × n) of groups of the first elements And 6 ₁₁ , ..., 6 _mn, the first group of adders 7 _1, 7 _2, ..., 7 _n, the first group of registers 8 _1, 8 _2, ... 8 _n, the first group of comparison circuits 9 _1, 9 _2, ... 9 _n, the second lement and 10, second adder 11, a second comparison circuit 12, a plurality of second registers 13 _1, 13 _2, ..., 13 _m, the third register 14, the start input 15, first group of output devices 17 _1, 17 _2, ..., 17 _m , the second output of the device 18, the output of each trigger 5 _ij (i = 1, 2, ..., m, j = 1, 2, ..., n) is connected to the first input of the same group of elements And 6 _ij , the second group of inputs of which is connected to output homonymous counters 4 _i, and an output connected to the input of the adder 7 of the same name _j, the output of which is connected to the first input of the same name of the first comparison circuit 9 _j, whose second input Connect the to the output of the same name of the first register 8 _j, the output of each first comparison circuit 9 _j is connected to the same name input of the second AND gate 10, the output of the second adder 11 is connected to the first input of the second comparison circuit 12, the second input of which is connected to the output of the third register 14, each yields register from the group of second registers 13 ₁ , 13 ₂ , ..., 13 _m are the first outputs of the device 17 ₁ , 17 ₂ , ..., 17 _m .

The disadvantage of this device is the low reliability, which is associated with asynchronous operation of the device blocks, and low speed.

The reasons that impede the achievement of the technical result indicated below include large hardware and time costs associated with the presence of m groups of third elements And, m groups of fourth elements And, the first and second delay elements and three elements I.

The technical result of the invention is to increase the reliability of the device, reduce hardware costs, increase the speed of the device and expand the functionality in terms of the possibility of setting acceptable ranges for the number of employees in each group of distribution options for employees.

The specified technical result in the implementation of the invention is achieved by the fact that in the device for modeling the work schedule of employees of the institution containing a clock pulse generator 1, a group of counters 4 ₁ , 4 ₂ , ..., 4 _m , a matrix (m × n) of triggers 5 ₁ , ..., 5 _mn , matrix (m × n) of groups of first elements AND 6 ₁₁ , ..., 6 _mn , group of first adders 7 ₁ , 7 ₂ , ..., 7 _n , group of first registers 8 ₁ , 8 ₂ , ..., 8 _n , group of first comparison schemes 9 ₁ , 9 ₂ , ..., 9 _n , the second element And 10, the second adder 11, the second comparison scheme 12, the group of second registers 13 ₁ , 13 ₂ , ..., 13 _m , the third register 14, start input 15, a group of the first outputs of the device 17 ₁ , 17 ₂ , ..., 17 _m , the second output of the device 18, and the output of each trigger 5 _ij (i = 1, 2, ..., m, j = 1, 2, ..., n ) is connected to the first input of the same group of elements And 6 _ij , the second group of inputs of which is connected to the output of the counter of the same name 4 _i , and the output is connected to the same input of the adder 7 _j , the output of which is connected to the first input of the same name of the first comparison circuit 9 _j , the second input of which connected to the output of the first register of the same name 8 _j , the output of each first comparison circuit 9 _{j is} connected n to the same input of the first group of inputs of the second element And 10, the output of the second adder 11 is connected to the first input of the second comparison circuit 12, the second input of which is connected to the output of the third register 14, the outputs of each register from the group of second registers 13 ₁ , 13 ₂ , ..., 13 _m are the first outputs of the device 17 ₁ , 17 ₂ , ..., 17 _m , an additional trigger of permission 2, a readiness trigger of result 3, an input for initial installation of the device 16, a third output of the device 19, a group of fourth registers 20 ₁ , 20 ₂ , ..., 20 _m , group of fifth registers 21 ₁ , 21 ₂ , ..., 21 _m , a group of third comparison circuits 22 ₁ , 22 ₂ , ..., 22 _m , and the input of the initial installation of the device 16 is connected to the inputs of the synchronous zero state by the second input of the trigger of permission 2, the second input of the trigger of readiness of result 3, the second inputs of the group of m second registers 13 ₁ , 13 ₂ , ..., 13 _m , the second inputs of the synchronous load of a group of m counters 4 ₁ , 4 ₂ , ..., 4 _m and the second input of the synchronous installation in the single state of the third register 14, the output of the generator 1 is connected to the synchronization inputs first trigger trigger permission 2, first in Odom trigger readiness outcome 3, the first inputs of the group of the m counters 4 _1, 4 _2, ... 4 _m, the first inputs of the group of m second registers 13 _1, 13 _2, ..., 13 _m, and the first input of the third register 14, the start input device 15 is connected to the third enable input of the trigger of permission 2, the output of which is connected to the third input of the enable of the first counter 4 ₁ and the first enable input of the first circuit 22 _{1 of the} group of third comparison circuits, the outputs of each i-th counter 4 _{i are} connected to the information inputs of the corresponding i -th register 13 _{i (i} = 1, 2, ..., m) groups of m second registers 13 _1, 13 _2, ... 13 _m with the same corresponding inputs of the second adder 11, the output of the second adder 11 is also connected to a fourth data inputs of the third register 14, the second input of the second AND gate 10 is connected to the output of the second comparison circuit 12 , the output of the second element And 10 is connected to the recording permission inputs by the third inputs of the group of m second registers 13 ₁ , 13 ₂ , ..., 13 _m and the third input of the third register 14, the outputs of each register 20 _{i of the} group of fourth registers 20 ₁ , 20 ₂ , ... 20 _m are connected to the fourth informational m inputs homonymous counters 4 _i (i = 1, 2, ..., m), whose outputs are also connected to second inputs of the same name of third comparison circuits 22 _i, the third inputs of which are connected to outputs of the same names fifth registers 21 _i, the output of each comparison circuit 22 _i is connected with the fifth boot input of the counter of the same name 4 _i (i = 1, 2, ..., m), the output of each comparison circuit 22 _i (i = 1, 2, ..., m-1) is also connected to the work enable input by the third input (i + 1) -th counter 4 _{i + 1} and the corresponding input of the first group of inputs of (i + 1) -th, (i + 2) -th - (m) -th comparison circuits 22 _{i + 1} , 22 _{i + 1} -22 _m , the comparison circuit 22 output is the _m It is connected to a fourth input of the synchronous setting in the zero state authorization trigger 2 and the third input of the synchronous state of installation in a single trigger result readiness 3, whose output is the second output of the device 18, the output of the third register 14 is the third output of device 19.

Figure 1 shows a diagram of the proposed device for modeling the work schedule of employees of the institution.

In Fig. 1, the following designations are adopted: a clock pulse generator (GTI) 1, a resolution trigger 2, a readiness trigger for result 3, a group of counters 4 ₁ , 4 ₂ , ..., 4 _m , a matrix (m × n) of triggers 5 ₁₁ , ..., 5 _mn , matrix (m × n) of groups of first elements AND 6 ₁₁ , ..., 6 _mn , group of first adders 7 ₁ , 7 ₂ , ..., 7 _n , group of first registers 8 ₁ , 8 ₂ , ..., 8 _n , group the first comparison circuits 9 ₁ , 9 ₂ , ..., 9 _n , the second element And 10, the second adder 11, the second comparison circuit 12, the group of the second registers 13 ₁ , 13 ₂ , ..., 13 _m , the third register 14, input start 15, the input of the initial installation of device 16, the group of first you device moves 17 ₁ , 17 ₂ , ..., 17 _m , second device output 18, third device output 19, group of fourth registers 20 ₁ , 20 ₂ , ..., 20 _m , group of fifth registers 21 ₁ , 22 ₂ , ..., 22 _m , a group of third comparison schemes 22 ₁ , 22 ₂ , ..., 22 _m .

The external input of the initial installation of the device 16 is connected to the inputs of the synchronous zero state by the second input of the trigger of permission 2, the second input of the trigger of readiness of result 3, the second inputs of the group of m second registers 13 ₁ , 13 ₂ , ..., 13 _m , the second inputs of the synchronous load of the group of m counters 4 ₁ , 4 ₂ , ..., 4 _m and the second input of the synchronous installation in a single state of the third register 14.

The output of the GTI generator 1 is connected to the synchronization inputs - the first input of the enable trigger 2, the first input of the readiness trigger 3, the first inputs of the group of m counters 4 ₁ , 4 ₂ , ..., 4 _m , the first inputs of the group of m second registers 13 ₁ , 13 ₂ , ..., 13 _m , the first input of the third register 14.

The start input of the device 15 is connected to the third enable input of the trigger of permission 2, the output of which is connected to the third input of the enable of the first counter 4 ₁ and the first enable input of the first circuit 22 _{1 of the} group of third comparison circuits.

The outputs of each i-th counter 4 _i (i = 1, 2, ..., m) are connected to the corresponding inputs of the same second adder 11 and to the information inputs of the corresponding i-th register 13 _{i of the} group of m second registers 13 ₁ , 13 ₂ , ... , 13 _m , the outputs of which are the first outputs of the device 17 ₁ , 17 ₂ , ..., 17 _m .

The output of each trigger 5 _ij (i = 1, 2, ..., m, j = 1, 2, ..., n) is connected to the first input of the same group of elements And 6 _ij , the second group of inputs of which is connected to the output of the counter of the same name 4 _i , and the output is connected to the input of the adder of the same name 7 _j , the output of which is connected to the first input of the same name of the first comparison circuit 9 _j , the second input of which is connected to the output of the same name of the first register 8 _j .

The output of each first comparison circuit 9 _{j is} connected to the same input of the first group of inputs of the second element And 10, the second input of which is connected to the output of the second comparison circuit 12. The output of the second adder 11 is connected to the fourth information inputs of the third register 14 and to the first input of the second comparison circuit 12 , the second input of which is connected to the output of the third register 14.

The output of the second element And 10 is connected to the recording permission inputs by the third inputs of the group of m second registers 13 ₁ , 13 ₂ , ..., 13 _m and the third input of the third register 14.

The outputs of each register 20 _{i of the} group of fourth registers 20 ₁ , 20 ₂ , ..., 20 _{m are} connected to the fourth information inputs of the counter of the same name 4 _i (i = 1, 2, ..., m), the outputs of which are also connected to the second inputs of the same third comparison circuits 22 _i , the third inputs of which are connected by the outputs of the same fifth registers 21 _i .

The output of each comparison circuit 22 _{i is} connected to the fifth input of the load of the same name counter 4 _i (i = 1, 2, ..., m), the output of each i-th comparison circuit 22 _i (i = l, 2, ..., m-1) is also connected to the work enable input by the third input of the (i + 1) th counter 4 _{i + 1} and the corresponding input of the first group of inputs of the (i + 1) th, (i + 2) th - (m) th comparison circuits 22 _{i +1} , 22 _{i + 1} -22 _m , the output of the comparison circuit 22m is also connected to the fourth input of the synchronous installation in the zero state of the enable trigger 2 and the third input of the synchronous installation in the single state of the ready trigger for result 3, the output of which is the second output of the device 18, the output of the third register 14 is the third output of the device 19.

The device allows, as a result of simulation, to determine the optimal work schedule for employees of the enterprise (workshop) with uneven loading at different time intervals (days of the week or month, with shift work during the day, etc.).

In the initial state, the values corresponding to the required number of employees required in the j-th interval (period, day) of the institution’s work are entered in the group of first registers 8 ₁ , 8 ₂ , ..., 8 _n . According to the work schedules, in triggers 5 _ij (i = 1, 2, ..., m, j = 1, 2, ..., n), 0 is written if in the i-th variant (i-th row in the matrix (m × n ) triggers) the employment of employees in the jth interval (the jth column in the matrix) is not provided, or 1 is written if the employment of employees in the jth interval is provided for in the i-th option, the code for the maximum possible number of employees is written in the third register 14 institutions, for example, all units are installed.

Counters 4 ₁ , 4 ₂ , ..., 4 _m form the current distribution of employees in accordance with possible employee work schedules. In the initial state, all counters 4 ₁ , 4 ₂ , ..., 4 _m are set to the initial state. The group of second registers 13 ₁ , 13 ₂ , ..., 13 _m retains the best option, which ensures the distribution of employees in accordance with work schedules. For example, a work schedule for employees with two days off:

Schedule (i) Days of the week (j) Mon VT CP Thurs PT Sat Sun BUT one one one one one 0 0 B one one one one 0 0 one AT one one one 0 0 one one G one one 0 0 one one one D one 0 0 one one one one E 0 0 one one one one one F 0 one one one one one 0

In this table, a value of 0 means that with this work schedule, a group of employees has a day off, and a value of 1 means a working day. In general, weekends may be non-consecutive and not necessarily two days each. In addition, it is possible to set a schedule taking into account shift work during the day, or work after two or three days, etc.

The group of fourth registers 20 ₁ , 20 ₂ , ..., 20 _m contains the number of employees with whom contracts are concluded with this i-th mode of operation, i.e. these are the initial values for the corresponding 4 _i counters. The group of fifth registers 21 ₁ , 21 ₂ , ..., 21 _m contains the maximum number of employees who can be employed in accordance with this i-th version of the schedule.

The proposed device for solving the assignment problem works as follows.

The operation of the device is based on enumerating all possible options for the distribution of employees in the acceptable ranges of groups and determining the best option among them according to the criteria for a minimum of the total number of employees when they meet the required numbers according to work schedules.

The pulses from the GTI 1 are constantly supplied to the synchronization inputs of the group of counters 4 _i , the group of second registers 13 _i and third register 14, the operating modes of which are set by the signals at the corresponding control inputs.

When a signal is input to the input of the initial installation of device 16 along the edge of the pulse from the GTI 1, the enable trigger 2, the readiness trigger for result 3, the group of second registers 13 ₁ , 13 ₂ , ..., 13 _{m are} set to zero; the third register 14 is set to the state all units (maximum code for the number of employees), and the initial states from the fourth registers 20 ₁ , 20 ₂ , ..., 20 _m are entered in the counters 4 ₁ , 4 ₂ , ..., 4 _n .

The operation of the device begins after applying the START signal to the input of the device 15, by which, in synchronization with the pulse from the GTI 1, the output of the trigger of permission 2 is set to a single state, the output of which is connected to the third input of the resolution of the account of the first counter 4 ₁ and the first resolution input of the first circuit 22 ₁ third comparison schemes.

At the following steps of the GTI 1, at the outputs of the group of counters 4 ₁ , 4 ₂ , ..., 4 _n , the current variant of the distribution of employees is formed in accordance with work schedules. Each counter 4 _i counts from the minimum code (set on the fourth register of the same name 20 _i ) to the maximum code (set on the fifth register of the same name 21 _i ).

Upon reaching each counter 4 _i binary code equal to the code of the same name of the fifth register 21 _i, the output of the same name of the third comparison circuit 22 _i is formed a single signal CC _i, which is supplied to the fifth input authorization entries titled counter 4 _i and the third input of resolution next invoice counter 4 _{i + 1} . This signal CC _i = 1 synchronously with the front of the pulse from the GTI 1 in the counter of the same name 4 _i loads the initial code value from the fourth register of the same name 20 _i (i = 1, 2, ..., m), and also increases the code value in the next counter 4 _{i + 1} (i = 1, 2, ..., m-1).

Since the third comparison schemes 22 ₁ , 22 ₂ , ..., 22 _{m are} connected by parallel intergroup transfer, a single signal CC _i at the output of the current third comparison circuit 22 _i is formed only with single signals in all previous comparison schemes 22 _k (k = 1, 2, ..., i-1).

From the output of counter 4 _{i, the} binary code through the open elements And 6 _ij (if the trigger of the same name 5 _{ij is} set to a single state) goes to the same input of the first adder 7 _j , at the outputs of which the total number of employees in the jth period of the institution’s work will be received. The result code from the first adder 7 _j goes to the first input of the first comparison circuit 9 _j , the second input of which receives the code from the output of the first register 8 _j with the value of the required number of employees in a given period of the institution.

A single signal at the output of the first comparison circuit 9 _j is formed only if the code at the output of the first adder 7 _{j is} greater than or equal to the code at the output of the first register of the same name 8 _j . The signal from the output of the first comparison circuit 9 _j goes to the same input of the second element And 10.

At the same time, the binary codes from the outputs of the counters 4 _i arrive at the inputs of the same name of the second adder 11. The result code from the second adder 11 is supplied to the first inputs of the second comparison circuit 12, the second inputs of which receive the code from the output of the third register 14.

A single signal at the output of the second comparison circuit 12 is formed only if the code at the output of the second adder 11 is less than or equal to the code at the output of the third register of the same name 14. The result of the comparison from the output of the second comparison circuit 12 is sent to the second input of the second element And 10.

If single signals are installed at all inputs of the second element And 10, then the signal EN = 1 is generated at its output to enable recording of the current version of the distribution of employees by work periods (the best option at the current time) from counters 4 ₁ , 4 ₂ , ..., 4 _m into the group of second registers 13 ₁ , 13 ₂ , ..., 13 _m and records the total number of required employees from the outputs of the second adder 11 to the third register 14.

Thus, on the second registers 13 ₁ , 13 ₂ , ..., 13 _m , codes of the numbers of the number of employees employed during periods of work corresponding to the i-th work schedule of employees (i = 1, 2, ..., m) will be fixed, and on the third register 14 total number of employees.

When generating a single signal CC _m = 1 at the output of the third comparison circuit 22 _m , in this case all single signals CC _i = 1 will also be generated, along the edge of the clock signal of generator 1, the enable trigger 2 is set to zero and the counter counting mode 4 ₁ stops and the readiness trigger of result 3 is set to a single state, as a result of which, at the output of the device 18, a signal is READY about the end of the device.

The result of the operation of the device are codes on the group of second registers 13 ₁ , 13 ₂ , ..., 13 _m and the third register 14, which can be removed from the first outputs of the device 17 ₁ , 17 ₂ , ..., 17 _m and the third output of the device 19.

In the proposed device, with a single signal EN = 1, a record of the distribution of employees by work period and a record of the total number of required employees are recorded synchronously along the front of the next clock signal, which increases the reliability compared to the prototype, which performs asynchronous recording of signals generated in the device.

In the proposed device, the clock cycle of the SI is determined by the total time - the switching time of one group of synchronous counters 4 _i , the delay time of the element And 6 _ij , the delay time of the adder 7 _i , the delay time of the comparison circuit 9 _i , the delay time of the element And 10 and the time of preset in the registers 13 _i or 14. In the proposed device, the installation time of the code at the outputs of the counters 4 _i is determined by the switching delay of only one group of synchronous counters, since the groups of counters are combined in parallel renosome, and in the prototype the counters are connected in series. In the proposed device, the total transit time of the clock signals is reduced by the delays of two elements from m groups of elements And, two delay elements and two elements I. In addition, in the proposed device, the increase in speed is achieved by eliminating the number of employees in each group of distribution options outside the specified allowable ranges employees.

In addition, in the proposed device, in contrast to the prototype, the amount of hardware costs is reduced due to the exclusion of 2m groups of AND elements, two delay elements and three AND elements.

The above information allows us to conclude that the proposed device for modeling the work schedule of employees of the institution has a regularity of nodes and connections and corresponds to the claimed technical result - increased reliability, reduced hardware costs, increased speed and expanded functionality in terms of the possibility of setting acceptable ranges for the number of employees in each group employee distribution options.

Claims (1)

A device for modeling the work schedule of employees of the institution, containing a clock generator 1, a group of counters 4 ₁ , 4 ₂ , ..., 4m, a matrix (m × n) of triggers 5 ₁₁ , ..., 5 _mn , a matrix (m × n) of groups of first elements And 6 ₁₁ , ..., 6 _mn , the group of the first adders 7 ₁ , 7 ₂ , ..., 7 _n , the group of the first registers 8 ₁ , 8 ₂ , ..., 8 _n , the group of the first comparison schemes 9 ₁ , 9 ₂ , ..., 9 _n , the second element And 10, the second adder 11, the second comparison circuit 12, the group of the second registers 13 ₁ , 13 ₂ , ..., 13 _m , the third register 14, the input of the start 15, the group of the first outputs of the device 17 ₁ , 17 ₂ , ..., 17 _m , second output of device 18 and the output of each trigger 5 _ij (i = 1, 2, ..., m, j = 1, 2, ..., n) is connected to the first input of the same group of elements And 6 _ij , the second group of inputs of which is connected to the output of the counter of the same name 4 _i and the output is connected to the same input of the adder 7 _j , the output of which is connected to the first input of the first comparison circuit of the same name 9 _j , the second input of which is connected to the output of the first register of the same name 8 _j , the output of each first comparison circuit 9 _{j is} connected to the same input of the first group of inputs second element And 10, the output of the second sum ra 11 is connected to the first input of the second comparison circuit 12, the second input of which is connected to the output of the third register 14, the outputs of each register of the group of second registers 13 _1, 13 _2, ... 13 _m are the first output element 17 _1, 17 _2, ..., 17 _m , characterized in that it additionally introduces a trigger of permission 2, a trigger of readiness of result 3, an input of the initial installation of device 16, a third output of device 19, a group of fourth registers 20 ₁ , 20 ₂ , ..., 20 _m , a group of fifth registers 21 ₁ , 21 ₂ , ..., 21 _m , a group of third comparison schemes 22 ₁ , 22 ₂ , ..., 22 _m , and the input the initial installation of the device 16 is connected to the inputs of the synchronous zero state by the second input of the trigger of permission 2, the second input of the trigger of readiness of result 3, the second inputs of the group of m second registers 13 ₁ , 13 ₂ , ..., 13 _m , the second inputs of the synchronous load of the group of m counters 4 ₁ , 4 ₂ , ..., 4m and the second input of the synchronous installation in the single state of the third register 14, the output of the generator 1 is connected to the synchronization inputs by the first input of the trigger trigger 2, the first input of the trigger ready result 3, the first inputs PP from m counters 4 ₁ , 4 ₂ , ..., 4m, the first inputs of the group of m second registers 13 ₁ , 13 ₂ , ..., 13 _m and the first input of the third register 14, the start input of the device 15 is connected to the third input of the permission trigger 2, the output of which is connected to the third enable input of the first counter 4 ₁ and the first enable input of the first circuit 22 _{1 of the} group of third comparison circuits, the outputs of each i-th counter 4 _{i are} connected to the information inputs of the corresponding i-th register 13 _i (i = 1 , 2, ..., m) groups of m second registers 13 ₁ , 13 ₂ , ..., 13 _m and with the corresponding one by the input inputs of the second adder 11, the output of the second adder 11 is also connected to the fourth information inputs of the third register 14, the second input of the second element And 10 is connected to the output of the second comparison circuit 12, the output of the second element And 10 is connected to the recording permission inputs by the third inputs of the group of m second registers 13 ₁ , 13 ₂ , ..., 13 _m and the third input of the third register 14, the outputs of each register 20 _{i of the} group of fourth registers 20 ₁ , 20 ₂ , ..., 20 _{m are} connected to the fourth information inputs of the same counter 4 _i (i = 1, 2, ..., m) whose outputs oedineny also to the second inputs of the same name of third comparison circuits 22 _i, the third inputs of which are connected to outputs of the same names fifth registers 21 _i, the output of each comparison circuit 2 _i coupled to a fifth input load homonymous counters 4 _i (i = 1, 2, ..., m), the output of each comparison circuit 22 _i (i = 1, 2, ..., m-1) is also connected to the work enable input by the third input of the (i + 1) -th counter 4 _{i + 1} and the corresponding input of the first group of inputs (i + 1) th, (i + 2) th - (m) th comparing circuits 22 _{i + 1,} 22 _{i + 1} -22 _m, the output comparison circuit 22 _m is also connected to a fourth input of the synchronous setting at zero th status latch resolution 2 and the third input of the synchronous setting in one state the flip-flop 3 readiness result, the output of which is the second output unit 18, the output of the third register 14 is the third output device 19.

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