[go: up one dir, main page]

DE60140603D1 - Verfahren und vorrichtung für die befehlssatzarchitektur mit dyadischen digitalen signalverarbeitungsbefehlen - Google Patents

Verfahren und vorrichtung für die befehlssatzarchitektur mit dyadischen digitalen signalverarbeitungsbefehlen

Info

Publication number
DE60140603D1
DE60140603D1 DE60140603T DE60140603T DE60140603D1 DE 60140603 D1 DE60140603 D1 DE 60140603D1 DE 60140603 T DE60140603 T DE 60140603T DE 60140603 T DE60140603 T DE 60140603T DE 60140603 D1 DE60140603 D1 DE 60140603D1
Authority
DE
Germany
Prior art keywords
instruction
set architecture
isa
instructions
dsp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60140603T
Other languages
English (en)
Inventor
Kumar Ganapathy
Ruban Kanapathipiillai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE60140603D1 publication Critical patent/DE60140603D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
DE60140603T 2000-01-31 2001-01-25 Verfahren und vorrichtung für die befehlssatzarchitektur mit dyadischen digitalen signalverarbeitungsbefehlen Expired - Lifetime DE60140603D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/494,608 US6446195B1 (en) 2000-01-31 2000-01-31 Dyadic operations instruction processor with configurable functional blocks
PCT/US2001/002627 WO2001055843A1 (en) 2000-01-31 2001-01-25 Method and apparatus for instruction set architecture having dyadic digital signal processing instructions

Publications (1)

Publication Number Publication Date
DE60140603D1 true DE60140603D1 (de) 2010-01-07

Family

ID=23965180

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60140603T Expired - Lifetime DE60140603D1 (de) 2000-01-31 2001-01-25 Verfahren und vorrichtung für die befehlssatzarchitektur mit dyadischen digitalen signalverarbeitungsbefehlen

Country Status (7)

Country Link
US (8) US6446195B1 (de)
EP (1) EP1257911B1 (de)
CN (1) CN1246771C (de)
AT (1) ATE450000T1 (de)
AU (1) AU2001231182A1 (de)
DE (1) DE60140603D1 (de)
WO (1) WO2001055843A1 (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10045546A1 (de) * 2000-09-14 2002-04-04 Infineon Technologies Ag Verfahren zur systemunabhängigen digitalen Auswertung von Mobilkommunikations-Empfangssignalen verschiedener Mobilfunkstandards
US6779106B1 (en) * 2000-09-28 2004-08-17 International Business Machines Corporation Apparatus and method for an enhanced integer divide in an IA64 architecture
US6883165B1 (en) 2000-09-28 2005-04-19 International Business Machines Corporation Apparatus and method for avoiding deadlocks in a multithreaded environment
US6912647B1 (en) 2000-09-28 2005-06-28 International Business Machines Corportion Apparatus and method for creating instruction bundles in an explicitly parallel architecture
US6799262B1 (en) 2000-09-28 2004-09-28 International Business Machines Corporation Apparatus and method for creating instruction groups for explicity parallel architectures
EP1334590B1 (de) * 2000-11-17 2006-10-11 Infineon Technologies North America Corp. Vorrichtungen und Verfahren zur Behandlung von RTP- und TCP-Datenverkehr
JP2002182693A (ja) * 2000-12-13 2002-06-26 Nec Corp オーディオ符号化、復号装置及びその方法並びにその制御プログラム記録媒体
US7055019B2 (en) * 2001-02-13 2006-05-30 Ellipsis Digital Systems, Inc. Matched instruction set processor systems and method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms
US7075976B1 (en) * 2001-03-19 2006-07-11 Cisco Technology, Inc. Tri-state transmitter
US7024441B2 (en) * 2001-10-03 2006-04-04 Intel Corporation Performance optimized approach for efficient numerical computations
US20030167460A1 (en) * 2002-02-26 2003-09-04 Desai Vipul Anil Processor instruction set simulation power estimation method
WO2004001752A1 (en) * 2002-06-24 2003-12-31 Lg Electronics Inc. Recording medium having data structure for managing reproduction of multiple title video data recorded thereon and recording and reproducing methods and apparatuses
US7024544B2 (en) * 2003-06-24 2006-04-04 Via-Cyrix, Inc. Apparatus and method for accessing registers in a processor
US9465611B2 (en) * 2003-10-02 2016-10-11 Broadcom Corporation Processor execution unit with configurable SIMD functional blocks for complex number operations
US7437401B2 (en) * 2004-02-20 2008-10-14 Altera Corporation Multiplier-accumulator block mode splitting
CN1658152B (zh) * 2004-02-20 2012-06-13 阿尔特拉公司 乘法器-累加器块模式划分
US7660841B2 (en) * 2004-02-20 2010-02-09 Altera Corporation Flexible accumulator in digital signal processing circuitry
US7933405B2 (en) * 2005-04-08 2011-04-26 Icera Inc. Data access and permute unit
TW200808067A (en) * 2006-07-31 2008-02-01 Univ Nat Cheng Kung Prediction module
US7543013B2 (en) * 2006-08-18 2009-06-02 Qualcomm Incorporated Multi-stage floating-point accumulator
CN100450937C (zh) * 2007-01-11 2009-01-14 常州爱思特净化设备有限公司 液体处理模块
US7917568B2 (en) * 2007-04-10 2011-03-29 Via Technologies, Inc. X87 fused multiply-add instruction
US20100153100A1 (en) * 2008-12-11 2010-06-17 Electronics And Telecommunications Research Institute Address generator for searching algebraic codebook
CN101562594B (zh) * 2009-05-25 2011-09-07 哈尔滨工业大学 基于流水线操作的相位因子结合电路
WO2012104674A1 (en) 2011-01-31 2012-08-09 Freescale Semiconductor, Inc. Integrated circuit device and method for determining an index of an extreme value within an array of values
EP2737972A1 (de) * 2012-11-28 2014-06-04 Sandvik Intellectual Property AB Schweißmaterial für Schweißplattierung
US9880842B2 (en) * 2013-03-15 2018-01-30 Intel Corporation Using control flow data structures to direct and track instruction execution
US10001995B2 (en) * 2015-06-02 2018-06-19 Intel Corporation Packed data alignment plus compute instructions, processors, methods, and systems
US10089078B2 (en) * 2016-09-23 2018-10-02 Stmicroelectronics S.R.L. Circuit for performing a multiply-and-accumulate operation
US10379854B2 (en) * 2016-12-22 2019-08-13 Intel Corporation Processor instructions for determining two minimum and two maximum values
US10509651B2 (en) * 2016-12-22 2019-12-17 Intel Corporation Montgomery multiplication processors, methods, systems, and instructions
US10467324B2 (en) * 2017-05-24 2019-11-05 Microsoft Technology Licensing, Llc Data packing techniques for hard-wired multiplier circuits
US11809798B2 (en) 2019-12-13 2023-11-07 Intel Corporation Implementing large multipliers in tensor arrays
US11656872B2 (en) 2019-12-13 2023-05-23 Intel Corporation Systems and methods for loading weights into a tensor processing block
CN112256330B (zh) * 2020-11-03 2021-11-09 中国人民解放军军事科学院国防科技创新研究院 用于加速数字信号处理的risc-v指令集扩展方法
CN112491282B (zh) * 2020-11-06 2021-10-01 东北电力大学 基于载波pwm的y源双级矩阵变换器调制方法
US20230034406A1 (en) * 2021-07-21 2023-02-02 Microsemi Soc Corp. Generating RTL for a Circuit Using DSP Blocks
US20230129750A1 (en) * 2021-10-27 2023-04-27 International Business Machines Corporation Performing a floating-point multiply-add operation in a computer implemented environment

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1549531A1 (de) * 1966-08-16 1971-04-01 Scient Data Systems Inc Digitale Rechenanlage
JPS51144142A (en) * 1975-06-06 1976-12-10 Hitachi Ltd Information processing
JPH01183736A (ja) * 1988-01-18 1989-07-21 Toshiba Corp 情報処理装置
US4969118A (en) 1989-01-13 1990-11-06 International Business Machines Corporation Floating point unit for calculating A=XY+Z having simultaneous multiply and add
US5204828A (en) 1989-02-10 1993-04-20 Intel Corporation Bus apparatus having hold registers for parallel processing in a microprocessor
JP2834837B2 (ja) * 1990-03-30 1998-12-14 松下電工株式会社 プログラマブルコントローラ
US5163139A (en) 1990-08-29 1992-11-10 Hitachi America, Ltd. Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions
US5241492A (en) * 1991-05-06 1993-08-31 Motorola, Inc. Apparatus for performing multiply and accumulate instructions with reduced power and a method therefor
US6121998A (en) 1992-02-19 2000-09-19 8×8, Inc. Apparatus and method for videocommunicating having programmable architecture permitting data revisions
US6154828A (en) 1993-06-03 2000-11-28 Compaq Computer Corporation Method and apparatus for employing a cycle bit parallel executing instructions
US5420809A (en) * 1993-11-30 1995-05-30 Texas Instruments Incorporated Method of operating a data processing apparatus to compute correlation
EP0660245A3 (de) 1993-12-20 1998-09-30 Motorola, Inc. Arithmetische Maschine
JP3322754B2 (ja) * 1994-05-17 2002-09-09 富士通株式会社 並列計算機
US5530663A (en) 1994-11-14 1996-06-25 International Business Machines Corporation Floating point unit for calculating a compound instruction A+B×C in two cycles
EP0795153A4 (de) * 1994-12-02 2001-11-14 Intel Corp Mikroprozessor mit packfunktion für zusammengesetzte operanden
US5692207A (en) * 1994-12-14 1997-11-25 International Business Machines Corporation Digital signal processing system with dual memory structures for performing simplex operations in parallel
US5680578A (en) 1995-06-07 1997-10-21 Advanced Micro Devices, Inc. Microprocessor using an instruction field to specify expanded functionality and a computer system employing same
JP2931890B2 (ja) 1995-07-12 1999-08-09 三菱電機株式会社 データ処理装置
US5825658A (en) * 1995-09-14 1998-10-20 Vlsi Technology, Inc. Method and a system for specifying and automatically analyzing multiple clock timing constraints in a VLSI circuit
US5768553A (en) 1995-10-30 1998-06-16 Advanced Micro Devices, Inc. Microprocessor using an instruction field to define DSP instructions
US6088783A (en) * 1996-02-16 2000-07-11 Morton; Steven G DPS having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word
US6247036B1 (en) 1996-01-22 2001-06-12 Infinite Technology Corp. Processor with reconfigurable arithmetic data path
US5949762A (en) * 1996-01-24 1999-09-07 Telebit Corporation Apparatus and method for processing multiple telephone calls
JP3658072B2 (ja) * 1996-02-07 2005-06-08 株式会社ルネサステクノロジ データ処理装置およびデータ処理方法
JPH09223098A (ja) * 1996-02-19 1997-08-26 Sega Enterp Ltd 画像拡張機能ボード及びこれを用いた電子装置
US5940785A (en) 1996-04-29 1999-08-17 International Business Machines Corporation Performance-temperature optimization by cooperatively varying the voltage and frequency of a circuit
DE19625569A1 (de) * 1996-06-26 1998-01-02 Philips Patentverwaltung Signalprozessor
WO1998006030A1 (en) * 1996-08-07 1998-02-12 Sun Microsystems Multifunctional execution unit
US5890013A (en) * 1996-09-30 1999-03-30 Intel Corporation Paged memory architecture for a single chip multi-processor with physical memory pages that are swapped without latency
US6061521A (en) 1996-12-02 2000-05-09 Compaq Computer Corp. Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle
US6058410A (en) 1996-12-02 2000-05-02 Intel Corporation Method and apparatus for selecting a rounding mode for a numeric operation
US5880984A (en) 1997-01-13 1999-03-09 International Business Machines Corporation Method and apparatus for performing high-precision multiply-add calculations using independent multiply and add instruments
US5909698A (en) 1997-03-17 1999-06-01 International Business Machines Corporation Cache block store instruction operations where cache coherency is achieved without writing all the way back to main memory
US6029267A (en) * 1997-11-25 2000-02-22 Lucent Technologies Inc. Single-cycle, soft decision, compare-select operation using dual-add processor
US6425070B1 (en) 1998-03-18 2002-07-23 Qualcomm, Inc. Variable length instruction decoder
JP3541669B2 (ja) * 1998-03-30 2004-07-14 松下電器産業株式会社 演算処理装置
US6088785A (en) * 1998-04-15 2000-07-11 Diamond Multimedia Systems, Inc. Method of configuring a functionally redefinable signal processing system
US6247113B1 (en) * 1998-05-27 2001-06-12 Arm Limited Coprocessor opcode division by data type
US6041400A (en) * 1998-10-26 2000-03-21 Sony Corporation Distributed extensible processing architecture for digital signal processing applications
US6282633B1 (en) 1998-11-13 2001-08-28 Tensilica, Inc. High data density RISC processor
CA2354541C (en) * 1998-12-21 2004-04-13 N2Power Inc. Boost converter with reduced switching loss
US6560694B1 (en) * 2000-01-14 2003-05-06 Advanced Micro Devices, Inc. Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode
US6675376B2 (en) * 2000-12-29 2004-01-06 Intel Corporation System and method for fusing instructions

Also Published As

Publication number Publication date
EP1257911B1 (de) 2009-11-25
US20030023833A1 (en) 2003-01-30
CN1246771C (zh) 2006-03-22
US20040093481A1 (en) 2004-05-13
CN1404586A (zh) 2003-03-19
AU2001231182A1 (en) 2001-08-07
US6772319B2 (en) 2004-08-03
US6988184B2 (en) 2006-01-17
US20030018881A1 (en) 2003-01-23
US20030023832A1 (en) 2003-01-30
US20030018882A1 (en) 2003-01-23
US6631461B2 (en) 2003-10-07
EP1257911A1 (de) 2002-11-20
WO2001055843A1 (en) 2001-08-02
US20060112259A1 (en) 2006-05-25
HK1051244A1 (en) 2003-07-25
US20060112260A1 (en) 2006-05-25
ATE450000T1 (de) 2009-12-15
US6446195B1 (en) 2002-09-03
US6643768B2 (en) 2003-11-04
EP1257911A4 (de) 2005-01-26

Similar Documents

Publication Publication Date Title
DE60140603D1 (de) Verfahren und vorrichtung für die befehlssatzarchitektur mit dyadischen digitalen signalverarbeitungsbefehlen
GB2429554A (en) Method and apparatus to vectorize multiple input instructions
ATE498158T1 (de) Umkonfigurierbares verarbeitungssystem und - verfahren
ATE342493T1 (de) Verfahren zum betätigen einer waage und waage
WO1999026132A3 (en) Processor configured to generate lookahead results from collapsed moves, compares and simple arithmetic instructions
TW200705266A (en) System and method wherein conditional instructions unconditionally provide output
AU2003272259A8 (en) Programmable rule processing apparatus for conducting high speed contextual searches and characterzations of patterns in data
GB0919120D0 (en) Apparatus and method for performing multiply accumulate operations
GB2413878B (en) Instructions to assist the processing of a cipher message
ATE463788T1 (de) Datenverarbeitungseinheit für anweisungen in geschachtelten schleifen
WO2004097633A3 (en) Method and apparatus for recovering data values in dynamic runtime systems
WO2003090067A3 (en) System for expanded instruction encoding and method thereof
DE602005025677D1 (de) Programmierbare datenverarbeitungsschaltung, die simd-befehle unterstützt
ATE458219T1 (de) Verfahren zur datenverarbeitung mit modularer potenzierung und dazugehörige vorrichtung
ATE438145T1 (de) Verfahren und vorrichtung zur mehrfachverarbeitungsausführung von computeranweisungen
ATE493704T1 (de) Verfahren und vorrichtung zur verwendung eines hilfsrechners zur befehlsvorausholung für einen hauptprozessor
ATE461480T1 (de) Verfahren und vorrichtung für befehlssatzarchitektur zur gleichzeitigen durchführung von primären und schatten- digitalsignalverarbeitungssubbefehlen
TW200636581A (en) Methods and apparatus for instruction set emulation
ATE384993T1 (de) Verfahren und vorrichtung zur operandenverarbeitung in einer prozessoreinheit
KR950033813A (ko) 데이타처리장치
DE60235429D1 (de) Ausgabe und Abschluss von Befehlen in einem Prozessor mit unterschiedlicher Pipelinetiefe
WO2006075286A3 (en) A processor and its instruction issue method
TW200741536A (en) Computer having dynamically-changeable instruction set in real time
MX2008000623A (es) Sistema y metodo para controlar multiples hilos de ejecucion de programa dentro de un procesador de hilos de ejecucion multiples.
WO2005103889A3 (en) Methods and apparatus for multi-processor pipeline parallelism

Legal Events

Date Code Title Description
8364 No opposition during term of opposition