CN107611152A - The method for packing of back-illuminated type cmos sensor - Google Patents

Abstract

The invention provides a packaging method for a back-illuminated CMOS sensor, comprising: a rewiring layer; a back-illuminated CMOS sensor structure fixedly connected to the second surface of the rewiring layer; a logic chip arranged on the rewiring layer the first surface of the first surface; the encapsulation material, covering the logic chip; the perforation, formed in the encapsulation material; the metal lead structure, fabricated in the perforation, to realize the rewiring layer, the back-illuminated The CMOS sensor structure is electrically connected to the logic chip. The present invention adopts the method of rewiring layer to realize the electrical connection between the back-illuminated CMOS sensor, the logic chip and the metal lead structure, and has the advantages of small packaging volume, high sensing performance and device reliability; The electrical lead-out of the rewiring layer can be achieved by making metal pillars in the packaging material, without the need for TSV and other processes, which can greatly save process costs.

Description

Packaging method of back-illuminated CMOS sensor

technical field

The invention belongs to the field of semiconductor packaging, in particular to a packaging method for a back-illuminated CMOS sensor.

Background technique

With the increasingly powerful functions of integrated circuits, higher performance and higher integration, and the emergence of new integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and in the value of the entire electronic system The proportion is increasing. At the same time, as the feature size of integrated circuits reaches the nanometer level, transistors are developing towards higher density and higher clock frequency, and packaging is also developing towards higher density.

Due to the advantages of miniaturization, low cost and high integration, as well as better performance and higher energy efficiency, fan-out wafer-level packaging (fowlp) technology has become a An important packaging method for high-demand mobile/wireless network and other electronic equipment is one of the most promising packaging technologies at present.

Existing image sensor chip packages usually have many disadvantages such as thicker thickness, higher cost of TSV process, easy breakage of metal wires, and lower overall yield rate.

In addition, image sensor chips, such as back-illuminated CMOS image sensor chips, usually need to be integrated with logic chips. The existing manufacturing method is to electrically connect a separately packaged image sensor chip to the logic chip through a SUB substrate. , and it is necessary to realize the electrical extraction of the device through the through-silicon via process. This packaging method makes the volume of the device larger, the assembly process is more complicated, and the cost of the TSV process is higher, resulting in a higher cost of the final product.

Based on the above, it is necessary to provide a packaging structure and packaging method that can effectively integrate back-illuminated CMOS sensors and logic chips, effectively reduce the volume of the packaging structure and device stability, and effectively reduce the cost.

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a packaging method for a back-illuminated CMOS sensor, which is used to solve the problem of large packaging volume of image sensor chips and logic chips in the prior art and low device stability. And the problem of low product yield.

In order to achieve the above object and other related objects, the present invention provides a packaging method for a back-illuminated CMOS sensor, the packaging method comprising: 1) providing a supporting substrate, and forming a separation layer on the surface of the supporting substrate; 2) Forming a metal lead structure on the separation layer; 3) providing a logic chip, adhering the logic chip on the separation layer, wherein the side of the logic chip having an electrical lead-out structure faces the separation layer; 4) packaging the logic chip with packaging material; 5) separating the packaging material and the supporting substrate based on the separation layer; 6) making a rewiring layer on the packaging material and the logic chip to realize an electrical connection between the logic chip and the metal lead structure; and 7) providing a back-illuminated CMOS sensor structure, and fixing the back-illuminated CMOS sensor structure to the rewiring layer to realize the back-illuminated CMOS sensor structure. The electrical connection between the illuminated CMOS sensor structure, the logic chip and the metal lead structure; wherein, the manufacturing method further includes the step of exposing the metal lead structure to the packaging material.

Preferably, the supporting substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate; the separation layer includes one of an adhesive tape and a polymer layer, so The polymer layer is first coated on the surface of the support substrate by a spin-coating process, and then cured and shaped by an ultraviolet curing or thermal curing process.

Preferably, the height of the metal lead structure is greater than the thickness of the logic chip.

Preferably, step 7) includes: 7-1) providing a wafer with an image sensor on the front side, after adhering the front side of the wafer to a protective layer, thinning the wafer from the back side; 7- 2) providing a transparent cover, and bonding the transparent cover to the back of the wafer; 7-3) peeling off the protective layer to expose the image sensor on the front of the wafer to obtain the back-illuminated and 7-4) fixing the side of the back-illuminated CMOS sensor structure with the image sensor exposed on the rewiring layer to realize the back-illuminated CMOS sensor structure, the logic chip and the The electrical connection between the above-mentioned metal lead structures.

Preferably, in step 7-1), the thickness of the wafer after thinning is not greater than 3 μm, so as to improve the photosensitive intensity of the backside of the image sensor.

Preferably, in step 7-2), the transparent cover is bonded to the back of the wafer based on a gold-tin bonding layer.

Preferably, step 4) the method of packaging the logic chip with packaging materials includes one of compression molding, transfer molding, liquid seal molding, vacuum lamination and spin coating, and the packaging materials include polyimide, One of silicone and epoxy resin.

Preferably, step 6) making the rewiring layer is alternately performing the following steps: using a chemical vapor deposition process or a physical vapor deposition process to form a dielectric layer on the plane of the logic chip and the packaging material, and engraving the dielectric layer Form a patterned dielectric layer by etching; form a metal layer on the surface of the patterned dielectric layer by chemical vapor deposition process, evaporation process, sputtering process, electroplating process or electroless plating process, and etch the metal layer to form Patterned metal wiring layers.

Preferably, the material of the dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phospho-silicate glass, and fluorine-containing glass, and the material of the metal wiring layer includes One or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

Preferably, the metal lead structure includes one of metal pillars, solder balls, and stacks of metal pillars and solder bumps.

Preferably, the method for exposing the metal lead structure to the packaging material is to thin the packaging material in step 4), step 5), step 6) or step 7).

As mentioned above, the packaging method of the back-illuminated CMOS sensor of the present invention has the following beneficial effects:

1) The present invention adopts the method of rewiring layer to realize the electrical connection between the back-illuminated CMOS sensor, the logic chip and the metal lead structure, which has the advantages of small packaging volume, high sensing performance and device reliability;

2) The present invention only needs to make metal pillars in the packaging material in advance to realize the electrical lead-out of the rewiring layer, without the need for silicon perforation and other processes, which can greatly save process costs;

3) The invention has a simple process, can effectively improve the packaging performance of back-illuminated CMOS sensors and logic chips, and has broad application prospects in the field of semiconductor packaging.

Description of drawings

1 to 15 are schematic structural diagrams of each step of the packaging method of the back-illuminated CMOS sensor of the present invention.

Component designation description

101 Supporting substrate

102 separation layer

103 metal lead structure

104 wafers

1041 image sensor

105 logic chip

106 Packaging material

107 rewiring layer

108 transparent cover

109 gold tin bonding layer

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 1 to Figure 15. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

As shown in FIGS. 1 to 15 , this embodiment provides a packaging method for a back-illuminated CMOS sensor. The packaging method includes:

As shown in FIG. 1 to FIG. 2 , step 1) is firstly performed to provide a support substrate 101 , and a separation layer 102 is formed on the surface of the support substrate.

As an example, the supporting substrate 101 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate. In this embodiment, the support substrate 101 is selected as a glass substrate. The glass substrate is relatively low in cost, easy to form the separation layer 102 on its surface, and can reduce the difficulty of the subsequent peeling process.

As an example, the separation layer 102 includes one of an adhesive tape and a polymer layer. The polymer layer is first coated on the surface of the support substrate 101 by a spin-coating process, and then made by an ultraviolet curing or thermal curing process. Curing and forming.

In this embodiment, the separation layer 102 is selected as an adhesive tape, the cost of the adhesive tape is relatively low, and it only needs to be lifted by applying a force in the subsequent separation process, and the adhesion and separation processes are relatively simple. The cost of the whole process can be greatly saved.

As shown in FIG. 3 , step 2) is then performed to form a metal lead structure 103 on the separation layer 102 .

As an example, the metal lead structure 103 includes one of metal pillars, solder balls, and stacks of metal pillars and solder bumps. The shape of the metal leads can be adjusted according to the design of the subsequent rewiring layer 107, and finally the image sensor chip 104 and the logic chip 105 are electrically drawn out to the surface of the packaging material 106 through the rewiring layer 107 without using Expensive through-silicon via technology can realize electrical extraction.

As an example, the height of the metal lead structure 103 is greater than the thickness of the logic chip 105 , so as to facilitate subsequent exposure of the metal lead structure 103 to the packaging material 106 .

In this embodiment, the metal lead structure 103 is selected as a copper column with good electrical conductivity, so as to further save the process cost.

As shown in Figure 4, then proceed to step 3), provide a logic chip 105, and adhere the logic chip 105 on the separation layer 102, wherein, the side of the logic chip 105 with the electrical lead-out structure is facing the separation layer. Layer 102.

The number of the logic chips 105 can also be one or two or more, which can be selected according to the performance requirements of the device.

As shown in FIG. 5 , proceed to step 4) to package the logic chip 105 with the package material 106 .

As an example, the method of packaging the logic chip 105 with the packaging material 106 includes one of compression molding, transfer molding, liquid seal molding, vacuum lamination and spin coating, and the packaging material 106 includes polyimide, One of silicone and epoxy resin.

As an example, the thickness of the encapsulation material 106 is at least greater than the thickness of the logic chip 105 .

As shown in FIG. 6 , step 5) is followed to separate the encapsulation material 106 and the support substrate 101 based on the separation layer 102 .

As an example, separation may be achieved by applying a force to lift the encapsulation material 106 away from the separation layer 102 .

As shown in FIG. 7 , as an example, after the separation, a step of thinning the backside of the packaging material 106 to expose the metal lead structure 103 to the packaging material 106 is also included.

As shown in FIG. 8 , step 6) is then performed to form a rewiring layer 107 on the packaging material 106 and the logic chip 105 to realize the electrical connection between the logic chip 105 and the metal lead structure 103 .

Specifically, making the rewiring layer 107 includes:

Step a), using a chemical vapor deposition process or a physical vapor deposition process to form a dielectric layer on the packaging material 106 and the logic chip 105, and etching the dielectric layer to form a patterned dielectric layer.

As an example, the material of the dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass. In this embodiment, the dielectric layer is selected as silicon oxide.

Step b), forming a metal layer on the surface of the patterned dielectric layer by using a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or an electroless plating process, and etching the metal layer to form a patterned metal layer wiring layer.

As an example, the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. In this embodiment, the material of the metal wiring layer is selected as copper.

It should be noted that the rewiring layer 107 may include a plurality of dielectric layers and a plurality of metal wiring layers stacked in sequence. According to the wiring requirements, the metal wiring layers of each layer may be realized by patterning each dielectric layer or making through holes. The interconnection between them is to realize the connection requirements of different functions.

As shown in FIGS. 9 to 14 , proceed to step 7), provide a back-illuminated CMOS sensor structure, and fix the back-illuminated CMOS sensor structure on the second surface of the rewiring layer 107 to realize the The electrical connection between the back-illuminated CMOS sensor structure, the logic chip 105 and the metal lead structure 103 .

As an example, step 6) includes:

As shown in FIGS. 9 to 11 , step 6-1) is first performed to provide a wafer 104 with an image sensor 1041 on the front side, and after adhering the front side of the wafer 104 to a protective layer 110, face the wafer 104 from the back side. The wafer 104 is thinned.

As an example, in step 7-1), the thickness of the wafer 104 after thinning is not greater than 3 μm, so as to increase the photosensitive intensity of the backside of the image sensor 1041 .

As shown in FIG. 12 , then proceed to step 7-2), providing a transparent cover 108 , and bonding the transparent cover 108 to the back of the wafer 104 .

As an example, in step 7-2), the transparent cover 108 is bonded to the backside of the wafer 104 based on the gold-tin bonding layer 109 . In this embodiment, the transparent cover 108 is selected as a glass cover.

As shown in FIG. 13 , step 7-3) is then carried out to peel off the protective layer 110 to expose the image sensor 1041 on the front side of the wafer 104 to obtain the back-illuminated CMOS sensor structure.

As shown in FIG. 14 , step 7-4) is finally carried out, and the side of the back-illuminated CMOS sensor structure with the image sensor 1041 exposed is fixed on the second surface of the rewiring layer 107 to realize the back-illuminated CMOS sensor structure. The electrical connection between the CMOS sensor structure, the logic chip 105 and the metal lead structure 103 .

In addition, the metal lead structure 103 can also be selected as a solder ball, and the final structure is shown in FIG. 15 .

As mentioned above, the packaging method of the back-illuminated CMOS sensor of the present invention has the following beneficial effects:

1) The present invention adopts the method of rewiring layer to realize the electrical connection between the back-illuminated CMOS sensor, the logic chip and the metal lead structure, which has the advantages of small packaging volume, high sensing performance and device reliability;

2) The present invention only needs to make metal pillars in the packaging material in advance to realize the electrical lead-out of the rewiring layer, without the need for silicon perforation and other processes, which can greatly save process costs;

3) The invention has a simple process, can effectively improve the packaging performance of back-illuminated CMOS sensors and logic chips, and has broad application prospects in the field of semiconductor packaging.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (11)

1. a packaging method of a back-illuminated CMOS sensor, characterized in that, the packaging method comprises: 1) providing a support substrate, forming a separation layer on the surface of the support substrate; 2) forming a metal lead structure on the separation layer; 3) providing a logic chip, adhering the logic chip on the separation layer, wherein the side of the logic chip having an electrical lead-out structure faces the separation layer; 4) Encapsulating the logic chip with an encapsulation material; 5) separating the encapsulation material and the support substrate based on the separation layer; 6) making a rewiring layer on the packaging material and the logic chip, so as to realize the electrical connection between the logic chip and the metal lead structure; and 7) Provide a back-illuminated CMOS sensor structure, and fix the back-illuminated CMOS sensor structure on the rewiring layer to realize the connection between the back-illuminated CMOS sensor structure, the logic chip and the metal lead structure. electrical connection between Wherein, the manufacturing method further includes the step of exposing the metal lead structure to the packaging material. 2. The packaging method of the back-illuminated CMOS sensor according to claim 1, characterized in that: the supporting substrate comprises glass substrates, metal substrates, semiconductor substrates, polymer substrates and ceramic substrates One; the separation layer includes one of an adhesive tape and a polymer layer, and the polymer layer is first coated on the surface of the support substrate by a spin coating process, and then cured and shaped by an ultraviolet curing or thermal curing process . 3 . The method for packaging a back-illuminated CMOS sensor according to claim 1 , wherein the height of the metal lead structure is greater than the thickness of the logic chip. 4 . 4. The packaging method of the back-illuminated CMOS sensor according to claim 1, characterized in that: step 7) comprises: 7-1) providing a wafer with an image sensor on the front side, after adhering the front side of the wafer to a protective layer, thinning the wafer from the back side; 7-2) providing a transparent cover, bonding the transparent cover to the back of the wafer; 7-3) peeling off the protective layer to expose the image sensor on the front side of the wafer, so as to obtain the back-illuminated CMOS sensor structure; and 7-4) Fix the side of the back-illuminated CMOS sensor structure with the image sensor exposed on the rewiring layer, so as to realize the connection between the back-illuminated CMOS sensor structure, the logic chip and the metal lead structure. electrical connections. 5. The packaging method of the back-illuminated CMOS sensor according to claim 4, characterized in that: in step 7-1), the thickness of the thinned wafer is not more than 3 μm, so as to improve the thickness of the image sensor. The intensity of the back light. 6 . The method for packaging a back-illuminated CMOS sensor according to claim 4 , wherein in step 7-2), the transparent cover is bonded to the back of the wafer based on a gold-tin bonding layer. 7. The method for encapsulating the back-illuminated CMOS sensor according to claim 1, characterized in that: step 4) adopting encapsulation material to encapsulate the method for the logic chip comprises compression molding, transfer molding, liquid seal molding, vacuum layer One of pressure coating and spin coating, the encapsulation material includes one of polyimide, silicone and epoxy resin. 8. the packaging method of the back-illuminated CMOS sensor according to claim 1 is characterized in that: step 6) making described rewiring layer is to alternately carry out the following steps: Using a chemical vapor deposition process or a physical vapor deposition process to form a dielectric layer on the plane of the logic chip and the packaging material, and etching the dielectric layer to form a patterned dielectric layer; A metal layer is formed on the surface of the patterned dielectric layer by chemical vapor deposition process, evaporation process, sputtering process, electroplating process or electroless plating process, and the metal layer is etched to form a patterned metal wiring layer. 9. The packaging method of the back-illuminated CMOS sensor according to claim 8, characterized in that: the material of the dielectric layer comprises epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing One or a combination of two or more of glass, and the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. 10. The packaging method of a back-illuminated CMOS sensor according to claim 1, wherein the metal lead structure comprises one of metal pillars, solder balls, and stacks of metal pillars and solder bumps . 11. The packaging method of integrated image sensor chip and logic chip according to claim 1, characterized in that: the method of exposing the metal lead structure to the packaging material is in step 4), step 5), and step 6 ) or step 7) to thin the packaging material.