Crafton et al., 2021 - Google Patents
Merged Logic and Memory Fabrics for AI WorkloadsCrafton et al., 2021
View PDF- Document ID
- 9256092599174491779
- Author
- Crafton B
- Spetalnick S
- Raychowdhury A
- Publication year
- Publication venue
- Proceedings of the 26th Asia and South Pacific Design Automation Conference
External Links
Snippet
As we approach the end of the silicon roadmap, we observe a steady increase in both the research effort toward and quality of embedded non-volatile memories (eNVM). Integrated in a dense array, eNVM such as resistive random access memory (RRAM), spin transfer torque …
- 230000015654 memory 0 title abstract description 38
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistance random access memory [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistance random access memory [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistance random access memory [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5641—Multilevel memory having cells with different number of storage levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computer systems based on biological models
- G06N3/02—Computer systems based on biological models using neural network models
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Yu et al. | RRAM for compute-in-memory: From inference to training | |
| Roy et al. | In-memory computing in emerging memory technologies for machine learning: An overview | |
| Yu et al. | Compute-in-memory chips for deep learning: Recent trends and prospects | |
| Ielmini et al. | In-memory computing with resistive switching devices | |
| Chakraborty et al. | Resistive crossbars as approximate hardware building blocks for machine learning: Opportunities and challenges | |
| Luo et al. | Accelerating deep neural network in-situ training with non-volatile and volatile memory based hybrid precision synapses | |
| Yu et al. | Emerging memory technologies: Recent trends and prospects | |
| Wu et al. | A 40nm low-power logic compatible phase change memory technology | |
| Du Nguyen et al. | Memristive devices for computing: Beyond CMOS and beyond von Neumann | |
| Yoon et al. | A 40-nm, 64-Kb, 56.67 TOPS/W voltage-sensing computing-in-memory/digital RRAM macro supporting iterative write with verification and online read-disturb detection | |
| Shim et al. | Investigation of read disturb and bipolar read scheme on multilevel RRAM-based deep learning inference engine | |
| Parveen et al. | HielM: Highly flexible in-memory computing using STT MRAM | |
| Wang et al. | Advances of embedded resistive random access memory in industrial manufacturing and its potential applications | |
| Chen et al. | Recent technology advances of emerging memories | |
| Yan et al. | iCELIA: A full-stack framework for STT-MRAM-based deep learning acceleration | |
| KR20220044643A (en) | Ultralow power inference engine with external magnetic field programming assistance | |
| Luo et al. | Ferroelectric tunnel junction based crossbar array design for neuro-inspired computing | |
| Shreya et al. | Energy-efficient all-spin BNN using voltage-controlled spin-orbit torque device for digit recognition | |
| Ma et al. | In-memory computing: The next-generation ai computing paradigm | |
| Amrouch et al. | Towards reliable in-memory computing: From emerging devices to post-von-neumann architectures | |
| Ham et al. | Low-Power $ V_ {\bf DD} $/3 Write Scheme With Inversion Coding Circuit for Complementary Memristor Array | |
| Jang et al. | Stochastic SOT device based SNN architecture for On-chip Unsupervised STDP Learning | |
| Zhang et al. | Array-level boosting method with spatial extended allocation to improve the accuracy of memristor based computing-in-memory chips | |
| Wang et al. | RSACIM: Resistance summation analog computing in memory with accuracy optimization scheme based on MRAM | |
| Pham et al. | STT-MRAM architecture with parallel accumulator for in-memory binary neural networks |