From 69c1dd12f6e8bb8993b9cfd4cfc526ad4713bca6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ole=20Kr=C3=BCger?= <ole.kruger@trili.tech>
Date: Wed, 7 Aug 2024 16:02:51 +0100
Subject: [PATCH] RISC-V: Constrain capabilities on Bus methods

---
 src/riscv/lib/src/machine_state/bus.rs | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/riscv/lib/src/machine_state/bus.rs b/src/riscv/lib/src/machine_state/bus.rs
index ac4bd3a6ba66..ee5da134318a 100644
--- a/src/riscv/lib/src/machine_state/bus.rs
+++ b/src/riscv/lib/src/machine_state/bus.rs
@@ -90,7 +90,7 @@ pub struct Bus<ML: main_memory::MainMemoryLayout, M: backend::ManagerBase> {
     memory: main_memory::MainMemory<ML, M>,
 }
 
-impl<ML: main_memory::MainMemoryLayout, M: backend::Manager> Bus<ML, M> {
+impl<ML: main_memory::MainMemoryLayout, M: backend::ManagerBase> Bus<ML, M> {
     /// Bind the Bus state to the allocated space.
     pub fn bind(space: backend::AllocatedOf<BusLayout<ML>, M>) -> Self {
         Self {
@@ -100,7 +100,10 @@ impl<ML: main_memory::MainMemoryLayout, M: backend::Manager> Bus<ML, M> {
     }
 
     /// Reset the bus state.
-    pub fn reset(&mut self) {
+    pub fn reset(&mut self)
+    where
+        M: backend::ManagerWrite,
+    {
         self.devices.reset();
         self.memory.reset();
     }
-- 
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