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[Security] Gemmini DMA may expose protected memory despite translation or access faults #418
Description
Description
I identified a potential memory-protection vulnerability in Gemmini RTL at commit 8c3f9923.
During RTL simulation, I observed that Gemmini DMA operations could return data from a protected memory region despite an address-translation or access-permission fault.
A corresponding CPU access was denied under the tested privilege configuration, while the accelerator-side operation still exposed the synthetic test data.
Expected Behavior
DMA requests must respect address-translation and memory-access permissions. Failed permission checks must prevent protected memory data from becoming observable.
Actual Behavior
Under the tested configuration, the accelerator returned protected memory data despite the expected access restrictions.
The page-fault and access-fault observations appear to share an underlying fault-handling issue.
Environment
- Gemmini revision:
8c3f9923 - Unmodified upstream RTL
- RTL simulation with privilege-separated memory-access tests
Responsible Disclosure
I previously requested a private security reporting channel in #407 on October 18, 2026, but have not received a response.
I have independently reproduced the behavior and can provide a minimal reproducer, RTL traces, and supporting evidence privately.
I am withholding exploitation-enabling details from this public report.
Could the maintainers confirm the appropriate security contact or enable GitHub Private Vulnerability Reporting?
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