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Commits on Sep 20, 2025
- fix file path parser error, support env file_path in WiresDef and Instance function
  cxhy
  committed
  df90324
Commits on Aug 24, 2025
Commits on Aug 12, 2025
- Update MANUAL.md
  cxhy
  authored
  26f084e
- Update README.md
  cxhy
  authored
  33a4b24
Commits on Aug 10, 2025
- Update README.md
  cxhy
  authored
  004901f
- Merge branch 'master' of github.com:cxhy/vcg
  cxhy
  committed
  ac51a96
- 1. add instance_manager unittest
  cxhy
  committed
  76447e0
Commits on Aug 9, 2025
- Update test_vcg_rule_manager.py
  cxhy
  authored
  9c22c01
- add log info
  cxhy
  committed
  4632dbc
- add vcg_rule_manager unittest and fix bug
  cxhy
  committed
  4914e04
- support regex in wire expression + fix signal rule bug
  cxhy
  committed
  80b7b48
Commits on Aug 6, 2025
- - Enable rule sharing between WiresDef and Instance
  cxhy
  committed
  8c39f60
- add lazy mode and greedy mode for WiresDef, default is greddy mode
  cxhy
  committed
  afd5a9a
Commits on Jul 31, 2025
- Update vcg_logger.py
  cxhy
  authored
  cb24e0e
- Update vcg_file_processor.py
  cxhy
  authored
  d217e4a
- Update vcg_execution_engine.py
  cxhy
  authored
  4054171
- Update vcg_exceptions.py
  cxhy
  authored
  9b65f66
- Update vcg_connect_manager.py
  cxhy
  authored
  02f7184
- Update vcg.py
  cxhy
  authored
  e5d260e
- Update VerilogPreprocess.py
  cxhy
  authored
  49b4c8d
- Update VerilogParser.py
  cxhy
  authored
  74d8f20
- Update VerilogLexer.py
  cxhy
  authored
  b05f8ac
- Update VerilogAst.py
  cxhy
  authored
  7c205eb
- Delete VerilogLexer.py
  cxhy
  authored
  acf1a82
- Add files via upload
  cxhy
  authored
  482dac3
- Create VerilogLexer.py
  cxhy
  authored
  44a6102
- Rename lexr.py to VerilogLexer.py
  cxhy
  authored
  94d6d15
- Update README.md
  cxhy
  authored
  88be67c
Commits on Sep 2, 2020
- Create lexr.py
  cxhy
  authored
  4434490
- Initial commit
  cxhy
  authored
  8b1b410

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